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Thanks, adding the picture will really help maintenance! So IIUC, the existing code is broken when there is no Secure->Non-Secure transition additional context saved? > > Signed-off-by: Torbj�rn SVENSSON > Signed-off-by: Yvan Roux > --- > gdb/arm-tdep.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++---- > 1 file changed, 58 insertions(+), 4 deletions(-) > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 50ec41a66b1..759dfd76ef6 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -3417,6 +3417,57 @@ arm_m_exception_cache (struct frame_info *this_frame) > /* Fetch the SP to use for this frame. */ > unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); > > + /* Exception entry context stacking as described into ARMv8-M (section B3.19) > + and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference Manuals. > + > + SP Offsets > + Without With > + Callee Regs Callee Regs Could make the description here (Without Callee Regs) a more obvious match of the one below (Additional State Ctx When transitioning from Secure to Non-secure)? > + > + +-------------------+ > + 0xA8 | | 0xD0 > + +===================+ --+ <-- Original SP > + 0xA4 | S31 | 0xCC | > + +-------------------+ | > + ... | Additional FP Ctx Here and elsewhere, I suggest Ctx -> Context > + +-------------------+ | > + 0x68 | S16 | 0x90 | > + +===================+ --+ > + 0x64 | Reserved | 0x8C | > + +-------------------+ | > + 0x60 | FPSCR | 0x88 | > + +-------------------+ | > + 0x5C | S15 | 0x84 | FP Ctx > + +-------------------+ | > + ... | > + +-------------------+ | > + 0x20 | S0 | 0x48 | > + +===================+ --+ > + 0x1C | xPSR | 0x44 | > + +-------------------+ | > + 0x18 | Return address | 0x40 | > + +-------------------+ | > + 0x14 | LR(R14) | 0x3C | > + +-------------------+ | > + 0x10 | R12 | 0x38 | State Ctx > + +-------------------+ | > + 0x0C | R3 | 0x34 | > + +-------------------+ | > + ... | > + +-------------------+ | > + 0x00 | R0 | 0x28 | > + +===================+ --+ > + | R11 | 0x24 | > + +-------------------+ | > + ... | > + +-------------------+ | Additional State Ctx > + | R4 | 0x08 | When transitioning from > + +-------------------+ | Secure to Non-secure > + | Reserved | 0x04 | > + +-------------------+ | > + | Magic signature | 0x00 | > + +===================+ --+ <-- New SP */ > + > /* With the Security extension, the hardware saves R4..R11 too. */ > if (exc_return && tdep->have_sec_ext && secure_stack_used > && (!default_callee_register_stacking || exception_domain_is_secure)) > @@ -3475,25 +3526,28 @@ arm_m_exception_cache (struct frame_info *this_frame) > if (tdep->have_sec_ext && !default_callee_register_stacking) > { > /* Handle floating-point callee saved registers. */ > - fpu_regs_stack_offset = 0x90; > + fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; > for (i = 8; i < 16; i++) > { > cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); > fpu_regs_stack_offset += 8; > } > > - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0xD0); > + arm_cache_set_active_sp_value (cache, tdep, > + unwound_sp + sp_r0_offset + 0xA8); > } > else > { > /* Offset 0x64 is reserved. */ > - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0x68); > + arm_cache_set_active_sp_value (cache, tdep, > + unwound_sp + sp_r0_offset + 0x68); > } > } > else > { > /* Standard stack frame type used. */ > - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0x20); > + arm_cache_set_active_sp_value (cache, tdep, > + unwound_sp + sp_r0_offset + 0x20); > } > > /* If bit 9 of the saved xPSR is set, then there is a four-byte Thanks, Christophe