From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 96609 invoked by alias); 8 Aug 2018 20:49:45 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 96599 invoked by uid 89); 8 Aug 2018 20:49:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=H*r:sk:w14-v6s, serious, representative, functioning X-HELO: mail-pl0-f67.google.com Received: from mail-pl0-f67.google.com (HELO mail-pl0-f67.google.com) (209.85.160.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 08 Aug 2018 20:49:42 +0000 Received: by mail-pl0-f67.google.com with SMTP id w14-v6so1539303plp.6 for ; Wed, 08 Aug 2018 13:49:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id; bh=GJr9IlIlQTtjU2irnUTkv7ADGqzVg3oZWvqb1LlTtHM=; b=E6X2R+n3PxncVEfhiCdS3wliyraupdrWhbGnYZaBnCEw9H3lJhqVwDic8bC6mTEhjX vFhK8ewltzE3Vq6ip8CI/6L5N3IqjTii6rBfvRuWCdnL/oIHh/wybsCxj+iDNsEhdNGo kw11KIneMrnci/aI3tPMieIZlzPSZ4ZoPrReGLzaTiICiKA0NpOsNN6OP7JQs86QQWue TJtIbbUXoImUkv85qAZqDE7OTekAwKYITqF+pUA9GUE/dhpgeG3+XdB/WEmtvXTF2CKn NVDGDQonBG+ZwSIvQP9BAlqhA4eUtMTnNIiu9uy/ykmECxsZ5+0bf5Oc119a1mNJP2R7 mNoA== Return-Path: Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id q65-v6sm11112665pfj.127.2018.08.08.13.49.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Aug 2018 13:49:40 -0700 (PDT) Date: Wed, 08 Aug 2018 20:49:00 -0000 X-Google-Original-Date: Wed, 08 Aug 2018 13:49:19 PDT (-0700) Subject: Re: [PATCH 5/5] RISC-V: Add configure support riscv*-linux*. In-Reply-To: <871sb8ahs9.fsf@tromey.com> CC: Jim Wilson , gdb-patches@sourceware.org From: Palmer Dabbelt To: tom@tromey.com Message-ID: X-SW-Source: 2018-08/txt/msg00182.txt.bz2 On Wed, 08 Aug 2018 10:29:26 PDT (-0700), tom@tromey.com wrote: >>>>>> "Jim" == Jim Wilson writes: > > Jim> * Makefile.in (ALLDEPFILES): Add riscv-linux-nat.c, riscv-linux-tdep.c. > > This doesn't mention the ALL_TARGET_OBS change. > > Jim> * NEWS: Mention new GNU/Linux RISC-V target. > > Eli should review this bit. > > Jim> * configure.host: Add riscv*-*-linux*. > Jim> * configure.nat: Add riscv*. > Jim> * configure.tgt: Add riscv*-*-linux*. > > These parts are ok. > > Jim> diff --git a/gdb/Makefile.in b/gdb/Makefile.in > Jim> index 8c744d70c0..280b3b1283 100644 > Jim> --- a/gdb/Makefile.in > Jim> +++ b/gdb/Makefile.in > Jim> @@ -752,6 +752,8 @@ ALL_TARGET_OBS = \ > Jim> ppc-sysv-tdep.o \ > Jim> ppc64-tdep.o \ > Jim> ravenscar-thread.o \ > Jim> + riscv-linux-nat.o \ > Jim> + riscv-linux-tdep.o \ > Jim> riscv-tdep.o \ > Jim> rl78-tdep.o \ > Jim> rs6000-aix-tdep.o \ > > I think only the tdep file should be listed here. > > ALL_TARGET_OBS is used when --enable-targets=all is given. > In this case, we would not want the riscv-linux-nat.o object to be > linked in, since we're not necessarily building on linux. > > Is riscv a 64-bit architecture? (I don't know.) If so, gdb still > splits 64-bit targets into a separate variable, I think in case one is > building on a 32-bit machine without a 64-bit integer type (or maybe if > you didn't want to use the extra memory to inflate a bunch of type > sizes, not sure). In this case you'd want to add the tdep file to > ALL_64_TARGET_OBS instead. RISC-V is actually a family of ISAs, not one specific ISA. There are 4 base ISAs: rv32e (16 32-bit registers), rv32i (32 32-bit registers), rv64i (32 64-bit registers), and rv128i (32 128-bit revisers). They all look very similar and we developed the ports together, so they share the vast majority of the source. Since they're so similar we try to make sure that the various toolchain components always support all of them (aside from rv128i, which nobody has started serious work on and is only a placeholder in the spec). To enable this support in BFD we decided to put both the 32-bit and 64-bit RISC-V targets in the list of 32-bit targets. This allows toolchains configured with the 32-bit tuples to generate code for the 64-bit targets, which when coupled with multilib gives you a functioning setup. I'd like to keep this behavior in GDB if possible, so "riscv32-unknown-elf-gdb" can debug rv64i-based targets. One of my goals is to rely as little as possible on the tuple so users don't have to go find and build a whole bunch of them -- whenever I'm a user I find that to be a pain. > I wonder if this 32/64 bit thing is needed any more. Part of our rationale for doing this was that if you can build GCC 7 (the first version we support), then your host probably has support for 64-bit integer types. Nobody else has seemed to notice yet, but there also aren't that many RISC-V users so we're far from a representative sample.