From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by sourceware.org (Postfix) with ESMTPS id E9C3A3858D37 for ; Thu, 6 Oct 2022 18:27:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E9C3A3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=dabbelt.com Received: by mail-pf1-x42d.google.com with SMTP id 3so1277833pfw.4 for ; Thu, 06 Oct 2022 11:27:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:from:to:cc:subject:date:message-id :reply-to; bh=gHEh0q0X0n1HH+ABVIxyW9IJ4oZubFr78Hnj3Qaf1/Q=; b=oW+5hXADiJBM8HAQ3PVmLwNA94JtcqI8Bv5Iq02G1k7P5/oZW822fy2r0J2yPhXqcn ufJ1RdURX7hSI7HT9wQN0eJtrNvUNxaPvzJICNm2G1OLAwg0XBAt/bKha24uSPo9O4hK EDDsXOlStQRJcQwMv6kPaFVAGYV96DnaUestnSw9rl0yMbeUhGPDIrv1wrJw24VrQTrz y9t2IVdq5EyndPrp7Pgf37NjvT+tMTBOLFZeEi3n5HzGZxu6V3lk9innSmbLf4g5XW9E 0kHzH9dz14CzEvhE2S8xyMjt0sICOLwLFqT9s/7K8D1EiafD3mkZXqDgOXccFGggXFak pZGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:to:from:cc :in-reply-to:subject:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=gHEh0q0X0n1HH+ABVIxyW9IJ4oZubFr78Hnj3Qaf1/Q=; b=g+iiHT9aaE5FZvqGWAh6XwA9vXKOCThL0UaZ6iE1q4nwd5QGMA7R1zIvrmEAbHjEH6 HxYhsdVOgWJviop4GANQZC4taKw0ezYDkNLqi+c4xo98OkF4q8PL2oQVaT9qPc80SgLg 5Z2z2NbyK6FdQdNuO0U4TEo+bCxGeVstKtlUrV0mxCgPbeP6/+pt9xJgLMnGnSCPKGuy 86LUKts+IS7CJDzeMvxEra/3H5IwgeA9ViwnKFkgXfI2DK+uP/Y2PGHtIhl3KjvzliHw tfFRxkdlBMcPirueeFo9//BRj5oa6PaZTRuizKaTXwWtXH3TAd+L1nj8LqanIDsXk+EG odCg== X-Gm-Message-State: ACrzQf1OMhTS9AcYOhSgTQicDnJGqM1U75D+0sOX5QG/4fBYrYj5p84S hR9dlyt4LzGx+cdWAg3f7GIYQCxjd86m7xVm X-Google-Smtp-Source: AMsMyM5JKRJcJnIlJJ61eRDCf8VLfbR3Ly89P2GEW04TSqqZkEHL2qvKCaY6Q3DR+mBjrf6LnMas8Q== X-Received: by 2002:a63:8843:0:b0:449:4ec9:df42 with SMTP id l64-20020a638843000000b004494ec9df42mr1032350pgd.38.1665080830305; Thu, 06 Oct 2022 11:27:10 -0700 (PDT) Received: from localhost (76-210-143-223.lightspeed.sntcca.sbcglobal.net. [76.210.143.223]) by smtp.gmail.com with ESMTPSA id f14-20020aa7968e000000b00537eacc8fa6sm1022361pfk.40.2022.10.06.11.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 11:27:09 -0700 (PDT) Date: Thu, 06 Oct 2022 11:27:09 -0700 (PDT) X-Google-Original-Date: Thu, 06 Oct 2022 11:27:07 PDT (-0700) Subject: Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions In-Reply-To: <0e52b6e0-b012-4e77-970c-ae3ba507adae@irq.a4lg.com> CC: gdb-patches@sourceware.org From: Palmer Dabbelt To: research_trasio@irq.a4lg.com, vapier@gentoo.org, aburgess@redhat.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Oct 2022 18:27:15 -0000 On Thu, 06 Oct 2022 09:14:37 PDT (-0700), research_trasio@irq.a4lg.com wrote: > On 2022/10/07 0:58, Palmer Dabbelt wrote: >> On Thu, 06 Oct 2022 03:33:00 PDT (-0700), research_trasio@irq.a4lg.com >> wrote: >>> Because of recent 'Zmmul' support, the simulator is now broken.  This is >>> caused by instruction classification changes: >>> >>> [Before] >>> -   INSN_CLASS_M     : multiply / divide >>> [After Zmmul] >>> -   INSN_CLASS_M     : divide >>> -   INSN_CLASS_ZMMUL : multiply >>> >>> The simulator checks the instruction class to execute an instruction: >>> >>> -   INSN_CLASS_I  : 'I' >>> -   INSN_CLASS_M  : 'M' (multiply / divide) >>> -   INSN_CLASS_A  : 'A' >>> >>> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that >>> instruction >>> class is not handled by the simulator. >>> >>> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a >>> testcase to test all RV32M instructions run without any faults. >>> --- >>>  sim/riscv/sim-main.c        |  1 + >>>  sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ >>>  2 files changed, 19 insertions(+) >>>  create mode 100644 sim/testsuite/riscv/m-ext.s >>> >>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c >>> index 30d2f1e1c9a..0156f791d4b 100644 >>> --- a/sim/riscv/sim-main.c >>> +++ b/sim/riscv/sim-main.c >>> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const >>> struct riscv_opcode *op) >>>      case INSN_CLASS_I: >>>        return execute_i (cpu, iw, op); >>>      case INSN_CLASS_M: >>> +    case INSN_CLASS_ZMMUL: >>>        return execute_m (cpu, iw, op); >>>      default: >>>        TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class); >>> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s >>> new file mode 100644 >>> index 00000000000..b85397a32a0 >>> --- /dev/null >>> +++ b/sim/testsuite/riscv/m-ext.s >>> @@ -0,0 +1,18 @@ >>> +# check that the RV32M instructions run without any fault. >>> +# mach: riscv >>> + >>> +.include "testutils.inc" >>> + >>> +    start >>> + >>> +    .option    arch, +m >>> +    mul    x0, x1, x2 >>> +    mulh    x0, x1, x2 >>> +    mulhu    x0, x1, x2 >>> +    mulhsu    x0, x1, x2 >>> +    div    x0, x1, x2 >>> +    divu    x0, x1, x2 >>> +    rem    x0, x1, x2 >>> +    remu    x0, x1, x2 >>> + >>> +    pass >> >> Reviewed-by: Palmer Dabbelt >> Acked-by: Palmer Dabbelt >> >> though as we're talking about in this meeting, I'm not actually a gdbsim >> maintainer so I'm not sure I can formally approve it. >> > > Palmer, > > I saw following files and thought you are one of the person who can > formally approve my patch. > > Quoting sim/MAINTAINERS: >> SIM Maintainers >> >> The simulator is part of the GDB project, so see the file >> gdb/MAINTAINERS for general information about maintaining these files.... >> common Frank Ch. Eigler >> * (target, then global maintainers) > > I know that Andrew and Palmer are RISC-V target maintainers of GDB so I > assumed you are responsible for this area. But it seems... no one knows > exactly. It seems very few people is interested in the simulator so... > well... for now, I will continue pinging until someone who thinks > responsible notices. Ah, I guess I wasn't looking close enough. I also didn't write the sim port, Mike Frysinger did and he's a sim gloabal maintainer so I'd generally just deferred to him on these things. +Mike and Andrew: I'm OK reviewing sim patches, at least for the stuff that's pretty much just ISA encoding. The port certainly needs some love and I don't really have the time to write the code, but I'm OK finding some time to review stuff if that's what's necessary for patches to land (though I'd be very happy to have someone else do the work, as usual ;)).