[Bug tdep/27015] ARC: "eret" value is collected from the wrong data in register cache

["mikematic@privacy-mail.top" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=27015

Mikematics <mikematic@privacy-mail.top> changed:

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--- Comment #25 from Mikematics <mikematic@privacy-mail.top> ---
I will have to get back to this later in the week.
I seem to get the feeling that No one has done this before.
Certainly not Microchip.
 asm("eret"); is a hack. but I guess it is why the default handler is in ASM.
Here is a list of other references you might want to check out.

Reference List:
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o, because either you are fine with the weak default _nmi_handler. Or it is
your responsibility to give a correct implementation of the _nmi_handler,
either as assembler or as .c code or a mixture of both, and it is your
responsibility to use the correct instructions depending on what you intend to
do. Either you are fine with the default prologue and epilogue and return
instruction or you have to do everything on your own. You can do whatever you
want and whatever you need, but you don't get any help.

For the other exception handlers, we got at least some help from the context
functions.

Speaking of those context functions, I start to get the impression that for a
returning and non-trivial NMI (which uses registers like v?/a?/t?/s?) you might
even need to save and restore any registers on your own. Because if those are
clobbered by the _nmi_handler there is nothing that restores them for the
normal program flow. The default prologue would save them, but if you are
having an assembler eret in the handler, you would skip the epilogue. So you
would need to implement something similar like the context functions or verify
that your nmi_handler does not clobber any register.

Is there nobody which has ever implemented a "continue from WTD / DMT timeout",
and maybe has that knowledge?



Meanwhile, I found in the "MIPS32 microAptiv UC Processor Core Family Software
User's Manual", that you definitely need an (optional) ERET for NMI Servicing.
It is in Figure 6.5 (see attached image). 

It seems, that at an NMI the processor completely resets, and goes through the
crt0.S startup code. That code first checks the NMI bit, and if it is set, it
jumps the _nmi_handler. 

Unfortunately, everything which tell you about the _nmi_handler, is the text
"NMI Service Code" inside a box with the dashed outline, followed by an arrow
to a box with ERET with the remark "(optional)".

Also, an eret corresponds to:
if SR[2]
  PC = ErrorEPC
else
  PC = EPC
SR[1] = 0
SR[2] = 0
LL = 0Note: We have SR[2] = STATUS register bit 2 = STATUS.ERL = Error level
bit = 1.


I really wonder whether maybe my previous suggestion is much easier

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