[Bug record/28057] New: FAIL: gdb.btrace/tsx.exp: speculation indication

["vries at gcc dot gnu.org" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=28057

            Bug ID: 28057
           Summary: FAIL: gdb.btrace/tsx.exp: speculation indication
           Product: gdb
           Version: HEAD
            Status: NEW
          Severity: normal
          Priority: P2
         Component: record
          Assignee: unassigned at sourceware dot org
          Reporter: vries at gcc dot gnu.org
  Target Milestone: ---

Recently I started to see this fail with trunk:
...
(gdb) record instruction-history^M
1          0x00000000004004ab <main+4>: call   0x4004b7 <test>^M
2          0x00000000004004c6 <test+15>:        mov    $0x1,%eax^M
3          0x00000000004004cb <test+20>:        ret    ^M
(gdb) FAIL: gdb.btrace/tsx.exp: speculation indication
...

Looking in older testlogs, I see instead:
...
(gdb) record instruction-history^M
1          0x00000000004004aa <main+4>: call   0x4004b6 <test>^M
2       ?  0x00000000004004b6 <test+0>: xbegin 0x4004c5 <test+15>^M
3       ?  0x00000000004004bc <test+6>: mov    $0x0,%eax^M
4          0x00000000004004c1 <test+11>:        xend   ^M
5          0x00000000004004c4 <test+14>:        ret    ^M
(gdb) PASS: gdb.btrace/tsx.exp: speculation indication
...

This FAIL doesn't seem to be due to a gdb regression, I'm running into the same
fail with gdb-10-branch branchpoint, while at the time when that was current, I
didn't see this failure.

I've got this processor:
...
model name      : Intel(R) Core(TM) i7-6600U CPU @ 2.60GHz
...
which according to
https://ark.intel.com/content/www/us/en/ark/products/88192/intel-core-i7-6600u-processor-4m-cache-up-to-3-40-ghz.html
is a "skylake" one.

Reading here (
https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions ):
...
In June 2021, Intel published a microcode update that further disables
TSX/TSX-NI on various Xeon and Core processor models from Skylake through
Coffee Lake and Whiskey Lake as a mitigation for unreliable behavior of a
performance counter in the Performance Monitoring Unit (PMU).[26] By default,
with the updated microcode, the processor would still indicate support for RTM
but would always abort the transaction.
...
it seems that the fail could be triggered by this microcode update.

Footnote refers to
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
.

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