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From: "clyon at gcc dot gnu.org" <sourceware-bugzilla@sourceware.org>
To: gdb-prs@sourceware.org
Subject: [Bug tdep/28829] New: ARM Cortex-M: cannot backtrace from interrupt handler
Date: Thu, 27 Jan 2022 13:11:31 +0000	[thread overview]
Message-ID: <bug-28829-4717@http.sourceware.org/bugzilla/> (raw)

https://sourceware.org/bugzilla/show_bug.cgi?id=28829

            Bug ID: 28829
           Summary: ARM Cortex-M: cannot backtrace from interrupt handler
           Product: gdb
           Version: HEAD
            Status: NEW
          Severity: normal
          Priority: P2
         Component: tdep
          Assignee: unassigned at sourceware dot org
          Reporter: clyon at gcc dot gnu.org
  Target Milestone: ---

Hello,

Playing with sample STM32 code on a board with Cortex-M33 and Security
extension (STM32L552) I put a breakpoint in SysTick_Handler
from
NUCLEO-L552ZE-Q/Examples/GTZC/GTZC_TZSC_MPCBB_TrustZone/NonSecure/Src/stm32l5xx_it.c:132

When I ask for a backtrace, with GDB trunk I get:
(gdb) bt
#0  SysTick_Handler ()
at [...]/stm32l5xx_it.c:132
Backtrace stopped: Cannot access memory at address 0xd034f8d6

If I apply the patches I posted recently to add support for FNC_RETURN on such
devices
(https://sourceware.org/pipermail/gdb-patches/2022-January/185127.html), I get:
(gdb) bt
#0  SysTick_Handler ()
at [...]/stm32l5xx_it.c:132
#1  <signal handler called>
#2  0x00000000 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)

which only partially better ;-)

When I single-step in gdb's arm_m_exception_cache, I notice that
sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
returns 0x2002ff78, but later in the same function
unwound_sp = arm_cache_get_prev_sp (cache, tdep);
returns 0x2002ff70.
Since the breakpoint is set after the prologue, I think I might need to add
something like
arm_scan_prologue (this_frame, cache);
but this leads to a crash.

Looking into arm_scan_prologue, I was surprised to see that arm_frame_is_thumb
returns false although the processor is Cortex-M (so thumb-only).
This is because t_bit == 0x1000000 and cpsr == 0xf, which is surprising?

I have access to the board only until tomorrow, so I'm dumping my findings here
in case I can get help very quickly or someone else picks up the problem later.

-- 
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             reply	other threads:[~2022-01-27 13:11 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-27 13:11 clyon at gcc dot gnu.org [this message]
2022-05-09  6:55 ` [Bug tdep/28829] " clyon at gcc dot gnu.org
2022-10-21 10:03 ` luis.machado at arm dot com
2022-10-21 10:08 ` clyon at gcc dot gnu.org
2022-10-21 12:05 ` torbjorn.svensson at st dot com
2022-10-21 12:10 ` luis.machado at arm dot com

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