From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 1A2573858425; Thu, 8 Sep 2022 14:02:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1A2573858425 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1662645730; bh=mG+02e26hqySqsb4+bhJ/qtBLA5nvrlWom7G8gi1JW0=; h=From:To:Subject:Date:In-Reply-To:References:From; b=eRrmvaB7p7zK+YzjBda+YPOQ8rloQhYpoDpDRwqQFv+vnuJbytNCvMX6LD1HF0CPX MSaprdTZFwRQ8PjgKpb4hug0Ly/wgMLFsMm9zDBR1Q9WvEGcKAQ7Y/AYwaiCU8GO3c bPnEfLRnSSouGO+H79wsWO+aQyCPryGAGaPW45aE= From: "rth at gcc dot gnu.org" To: gdb-prs@sourceware.org Subject: [Bug gdb/29421] Extend aarch64 pauth xml for gdbstub and kernel mode Date: Thu, 08 Sep 2022 14:02:07 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gdb X-Bugzilla-Component: gdb X-Bugzilla-Version: HEAD X-Bugzilla-Keywords: X-Bugzilla-Severity: enhancement X-Bugzilla-Who: rth at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: luis.machado at arm dot com X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D29421 --- Comment #9 from Richard Henderson --- Comment on attachment 14317 --> https://sourceware.org/bugzilla/attachment.cgi?id=3D14317 Improve PAC support for bare metal aarch64 >- int cmask_num =3D AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base); >- CORE_ADDR cmask =3D frame_unwind_register_unsigned (this_frame, cma= sk_num); >+ /* Default bare metal case. We remove the top 16 bits. */ >+ CORE_ADDR cmask =3D 0xffff000000000000; This is incorrect. It's the most common memory configuration, sure, but it's certainly not the only one. The mask that the native linux case has been providing is built from a combination of fields in TCR_EL1: T0SZ, TBI0, TG0. This is why I suggested that qemu provide the same information build from the corresponding fields for the high-half of the address space: T1SZ, TBI1, TG1. And the similar but different fields in TCR_EL{2,3} when the cpu is in those modes. Note that bit 55 of the address may *always* be used to select the "high" or "low" half of the address space. --=20 You are receiving this mail because: You are on the CC list for the bug.=