From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 0B27B3858C98; Mon, 25 Dec 2023 01:52:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0B27B3858C98 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1703469147; bh=n1HVcWfV5D9hvMpRdJaJNTtAb5c7dAcgKF5jSRzrh94=; h=From:To:Subject:Date:In-Reply-To:References:From; b=NEojTzL6pus+K5bnV9yWicOQcFxkV/E+Izs/KQffGJItR2Hb9DLLZpthAhqxBQgdL JbbrvM9GWPtvz5bEVGcUTwv/9Opvjtz608WL0QcQOg+Emnp9rHJLOtm5vbuNQCRCq0 +fyuQ1cvgoIEuRtA90QIOzQrvivKtJ+tkXC8OtfI= From: "vapier at gentoo dot org" To: gdb-prs@sourceware.org Subject: [Bug sim/29869] sim: align sim register numbers with gdb register numbers Date: Mon, 25 Dec 2023 01:52:21 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gdb X-Bugzilla-Component: sim X-Bugzilla-Version: unknown X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: vapier at gentoo dot org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: vapier at gentoo dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D29869 --- Comment #4 from Mike Frysinger --- on the sim side, the key is to start with CPU_REG_FETCH & CPU_REG_STORE. t= hose set the callbacks for gdb to read/write registers via register number. ports with sim headers: aarch64 arm bfin cr16 d10v frv ft32 h8300 lm32 m32c ppc riscv rl78 rx sh ports w/out gdb support so don't super care: example-synacor mcore pru ports that copy & paste register numbers between gdb & sim so they're the s= ame: avr (AVR_xxx_REGNUM) bpf (BPF_Rxx) iq2000 (xxx_REGNUM) m32r (xxx_REGNUM) -- although it seems they aren't completely in sync m68hc11 (xxx_REGNUM) microblaze (NUM_REGS) mn10300 (struct _state.regs & xxx_REGNUM) moxie (struct moxie_regset.regs & xxx_REGNUM) msp430 (struct msp430_cpu_state.regs & MSP430_xxx_REGNUM) v850 (struct _v850_regs.regs & .sregs & E_xxx_REGNUM) ports w/gdb port & w/out sim headers that i'm not sure if/how they work: cris erc32(sparc) mips(many ISAs) or1k ppc --=20 You are receiving this mail because: You are on the CC list for the bug.=