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From: "rajesh.palla at amd dot com" <sourceware-bugzilla@sourceware.org>
To: gdb-prs@sourceware.org
Subject: [Bug gdb/30825] GDB doesn't send Hg packet when switching the
 inferiors
Date: Wed, 06 Sep 2023 04:29:59 +0000
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https://sourceware.org/bugzilla/show_bug.cgi?id=3D30825

--- Comment #2 from Palla, Rajesh <rajesh.palla at amd dot com> ---
This is the new target we added for AMD cores.
pc_unwind function is similar to default pc_unwind() except that it invalid=
ates
the cache when there is a change in the inferior.

static CORE_ADDR aiengine_unwind_pc (struct gdbarch *gdbarch, struct frame_=
info
*next_frame)
{
  gdb_byte buf[4];
  struct inferior *inf =3D current_inferior ();
  if (inf->pid !=3D prev_pid){
    prev_pid =3D inf->pid;
    get_current_regcache()->invalidate(gdbarch_pc_regnum (gdbarch));
  }
  frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
  return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_p=
tr);
}


Couple of questions:
1. When I tried to debug "arm arch", I see the Hg packets are sent every ti=
me
we switch the inferior without doing any operation. (see log.txt attached)
2. In our case, I don't see Hg packet being sent lazily when we give 'c&'
command. See the below log. But for other commands like mem read, I see Hg
packet being sent.

----(gdb) infe 1
GDB -> $Hgp1.1#af
GDB <- $OK#9a
GDB -> $g#67
GDB <- $0000....#df
----(gdb) infe 2
----(gdb) c &
GDB -> $vCont;c:p2.-1#10
GDB <- $OK#9a
----(gdb) infe 1
----(gdb) b producer
GDB -> $m280,4#67
GDB <- $00000000#80
GDB -> $Z0,280,4#b0
GDB <- $OK#9a

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