From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E182E3846401; Wed, 24 Apr 2024 20:16:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E182E3846401 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1713989764; bh=GGz7waxxTK9AEmGUnOlkb+Wjo3+wMYZtSBPXmDqQXPI=; h=From:To:Subject:Date:In-Reply-To:References:From; b=UHRnqNQl0qj2FOjNPxa8cfkIEIXtnyWUOF2gmYLXI0NlsACKoCpVN19J77ettbtIC VbMXO+A88yU7LT6oggxzKA2o/UHIus4ROgKJZl5WB0BdrNZ/pP5JQAkXULfOFcy3U2 /ZL8TzDAIiS8ioj+f/zhbT/3v6j4HlXUNQpKNjgo= From: "Tadej.Pecar@elaphe-ev.com" To: gdb-prs@sourceware.org Subject: [Bug tdep/31681] [powerpc] presence of SPE disables VLE instruction decoding Date: Wed, 24 Apr 2024 20:16:04 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gdb X-Bugzilla-Component: tdep X-Bugzilla-Version: HEAD X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: Tadej.Pecar@elaphe-ev.com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D31681 --- Comment #3 from Tadej Pe=C4=8Dar --- A quick hack that disables the SPE check, provides VLE variant & drops supp= ort for VLE / non-VLE mixing in ppc-dis.c seems to get the disassembly going, b= ut this obviously can't be considered a final solution. Need to clean it up. diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 23397d0..6a2d943 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -3506,6 +3506,8 @@ static struct ppc_variant variants[] =3D bfd_mach_ppc_7400, &tdesc_powerpc_7400}, {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, bfd_mach_ppc_e500, &tdesc_powerpc_e500}, + {"vle", "Motorola PowerPC VLE", bfd_arch_powerpc, + bfd_mach_ppc_vle, &tdesc_powerpc_e500}, /* 64-bit */ {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, @@ -7565,7 +7567,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) which looks at each instruction and determines which unit (and which version of it) can execute it. Grovel through the section looking for relevant e500 APUs. */ - +#if 0 if (bfd_uses_spe_extensions (info.abfd)) { arch =3D info.bfd_arch_info->arch; @@ -7573,7 +7575,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) bfd_default_set_arch_mach (&abfd, arch, mach); info.bfd_arch_info =3D bfd_get_arch_info (&abfd); } - +#endif /* Find a default target description which describes our register layout, if we do not already have one. */ if (! tdesc_has_registers (tdesc)) diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index d97137d..a5694c4 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -297,14 +297,14 @@ get_powerpc_dialect (struct disassemble_info *info) dialect =3D private_data (info)->dialect; /* Disassemble according to the section headers flags for VLE-mode. */ - if (dialect & PPC_OPCODE_VLE - && info->section !=3D NULL && info->section->owner !=3D NULL - && bfd_get_flavour (info->section->owner) =3D=3D bfd_target_elf_flav= our - && elf_object_id (info->section->owner) =3D=3D PPC32_ELF_DATA - && (elf_section_flags (info->section) & SHF_PPC_VLE) !=3D 0) +// if (dialect & PPC_OPCODE_VLE +// && info->section !=3D NULL && info->section->owner !=3D NULL +// && bfd_get_flavour (info->section->owner) =3D=3D bfd_target_elf_fl= avour +// && elf_object_id (info->section->owner) =3D=3D PPC32_ELF_DATA +// && (elf_section_flags (info->section) & SHF_PPC_VLE) !=3D 0) return dialect; - else - return dialect & ~ PPC_OPCODE_VLE; +// else +// return dialect & ~ PPC_OPCODE_VLE; } /* Handle -m and -M options that set cpu type, and .machine arg. */ --=20 You are receiving this mail because: You are on the CC list for the bug.=