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From: "Tadej.Pecar@elaphe-ev.com" <sourceware-bugzilla@sourceware.org>
To: gdb-prs@sourceware.org
Subject: [Bug tdep/31681] New: [powerpc] presence of SPE disables VLE
 instruction decoding
Date: Wed, 24 Apr 2024 13:33:23 +0000
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X-Bugzilla-Product: gdb
X-Bugzilla-Component: tdep
X-Bugzilla-Version: HEAD
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https://sourceware.org/bugzilla/show_bug.cgi?id=3D31681

            Bug ID: 31681
           Summary: [powerpc] presence of SPE disables VLE instruction
                    decoding
           Product: gdb
           Version: HEAD
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: tdep
          Assignee: unassigned at sourceware dot org
          Reporter: Tadej.Pecar@elaphe-ev.com
  Target Milestone: ---

On embedded PowerPC platforms with VLE instruction set (powerpc:vle) the
presence of SPE APU extension overrides the actual architecture to
powerpc:e500.

The architecture is detected correctly as `powerpc:vle` in bfd from compiler
provided section flags (check performed by `_bfd_elf_ppc_set_arch()` at
elf32-ppc.c )

`rs6000_gdbarch_init()` at rs6000-tdep.c then manually parses the apuinfo
section to determine if SPE APU is present and overrides the detected
architecture.

`info->abfd->archinfo` and `info->bfd_arch_info` are out of sync as a resul=
t of
this and may be source of additional bugs.

Even after user overrides to `powerpc:vle` the `maint print arch` displays `
bfd_arch_info =3D powerpc:e500` and the disassembler doesn't properly parse=
 the
instructions (treating them as non-VLE).

The VLE + SPE combination is possible on e200z3/4/6/7 cores (MPC5777C, MPC5=
775K
being the concrete examples).

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