[Bug sim/31915] New: gdb sim for riscv mishandle breakpoints, skips original instruction under ebreak

[Bug sim/31915] New: gdb sim for riscv mishandle breakpoints, skips original instruction under ebreak

[zelenski at cs dot stanford.edu]

https://sourceware.org/bugzilla/show_bug.cgi?id=31915

            Bug ID: 31915
           Summary: gdb sim for riscv mishandle breakpoints, skips
                    original instruction under ebreak
           Product: gdb
           Version: 14.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: sim
          Assignee: unassigned at sourceware dot org
          Reporter: zelenski at cs dot stanford.edu
                CC: vapier at gentoo dot org
  Target Milestone: ---

Created attachment 15585
  --> https://sourceware.org/bugzilla/attachment.cgi?id=15585&action=edit
Script show broken gdb and fixed version

gdb sim debugging bare-metal riscv program. Set breakpoint at address 0xblah.
When breakpoint is hit, the original instruction at address 0xblah is skipped.
I believe this is due to ebreak overwrite at 0xblah. When hit ebreak, expected
handling would restore the original at 0xblah and reissue instruction, but sim
mistakenly advances to 0xblah+4 which skips execution of original. This bug in
simulator seems to affect any use of breakpoints (severity of consequences vary
based on content of skipped instruction)

Excerpt from sim/riscv/sim-main.c below.
Edit line 628 to remove the "+4" seems to correct problem.

   625      case MATCH_EBREAK:
   626        TRACE_INSN (cpu, "ebreak;");
   627        /* GDB expects us to step over EBREAK.  */
   628        sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc+4, sim_stopped,
   629                         SIM_SIGTRAP);
   630        break;

Attachment shows gdb skipping instruction at breakpoint and again with above
fix applied showing that instruction is correctly executed

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[Bug sim/31915] gdb sim for riscv mishandle breakpoints, skips original instruction under ebreak

[zelenski at cs dot stanford.edu]

https://sourceware.org/bugzilla/show_bug.cgi?id=31915

Julie Zelenski <zelenski at cs dot stanford.edu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |zelenski at cs dot stanford.edu

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[Bug sim/31915] gdb sim for riscv mishandle breakpoints, skips original instruction under ebreak

[zelenski at cs dot stanford.edu]

https://sourceware.org/bugzilla/show_bug.cgi?id=31915

--- Comment #1 from Julie Zelenski <zelenski at cs dot stanford.edu> ---
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 250791634a1..ef81dfc1750 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -625,7 +625,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct
riscv_opcode *op)
     case MATCH_EBREAK:
       TRACE_INSN (cpu, "ebreak;");
       /* GDB expects us to step over EBREAK.  */
-      sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc + 4, sim_stopped,
+      sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped,
                       SIM_SIGTRAP);
       break;
     case MATCH_ECALL:

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