From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 112770 invoked by alias); 17 Dec 2015 11:31:01 -0000 Mailing-List: contact gdb-testers-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-testers-owner@sourceware.org Received: (qmail 112758 invoked by uid 89); 17 Dec 2015 11:31:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.9 required=5.0 tests=AWL,BAYES_00 autolearn=ham version=3.3.2 spammy=weaken, Hx-languages-length:2070 X-HELO: kwanyin.sergiodj.net Received: from kwanyin.sergiodj.net (HELO kwanyin.sergiodj.net) (176.31.208.32) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 17 Dec 2015 11:30:59 +0000 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [binutils-gdb] [AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions. From: sergiodj+buildbot@redhat.com To: gdb-testers@sourceware.org Message-Id: <40d16a76c781bc9951d22ee359e07c6c240b81ba@gdb-build> Date: Thu, 17 Dec 2015 11:31:00 -0000 X-SW-Source: 2015-q4/txt/msg10294.txt.bz2 *** TEST RESULTS FOR COMMIT 40d16a76c781bc9951d22ee359e07c6c240b81ba *** Author: Matthew Wahab Branch: master Commit: 40d16a76c781bc9951d22ee359e07c6c240b81ba [AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions. ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch set adds the 16-bit Adv.SIMD vector and scalar instructions to binutils, making them available when both +simd and +fp16 architecture extensions are enabled. The series also adds support for a new vector type, 2H, used by the FP16 scalar pairwise instructions. The patches in this series: - Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding routines. - Add FP16 instructions in the group Vector Three Register Same. - Add FP16 instructions in the group Scalar Three Register Same. - Add FP16 instructions in the group Vector Two Register Misc. - Add FP16 instructions in the group Scalar Two Register Misc. - Add FP16 instructions in the group Vector Indexed Element. - Add FP16 instructions in the group Scalar Indexed Element. - Add FP16 instructions in the group Adv.SIMD Across Lanes. - Add FP16 instructions in the group Adv.SIMD Modified Immediate. - Rework some code for handling vector types to weaken its assumptions about available vector-types. - Add support for the 2H vector type. - Add FP16 instructions in the group Adv.SIMD Scalar Pairwise. - Add FP16 instructions in the group Adv.SIMD Shift By Immediate. - Add a FP16 instructions in the group Adv.SIMD Scalar Shift By Immediate. This patch adds the feature macro SIMD_F16 to the AArch64 encoding/decoding routines. It is used to decide when the new instructions are available to the assembler and is true when both +simd and +fp16 are selected. opcodes/ 2015-12-14 Matthew Wahab * aarch64-tbl.h (aarch64_feature_simd_f16): New. (SIMD_F16): New. Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f