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From: gdb-buildbot@sergiodj.net
To: gdb-testers@sourceware.org
Subject: [binutils-gdb] x86: replace NoRex64 on VEX-encoded insns
Date: Mon, 16 Mar 2020 14:49:45 -0400 [thread overview]
Message-ID: <4ed21b58d4b8331806b9e88da18898235942f425@gdb-build> (raw)
*** TEST RESULTS FOR COMMIT 4ed21b58d4b8331806b9e88da18898235942f425 ***
commit 4ed21b58d4b8331806b9e88da18898235942f425
Author: Jan Beulich <jbeulich@suse.com>
AuthorDate: Fri Mar 6 08:53:18 2020 +0100
Commit: Jan Beulich <jbeulich@suse.com>
CommitDate: Fri Mar 6 08:53:18 2020 +0100
x86: replace NoRex64 on VEX-encoded insns
When the template specifies any of the possible VexW settings, we can
use this instead of a separate NoRex64 to suppress the setting of REX_W.
Note that this ends up addressing an inconsistency between VEX- and
EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former
avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a
64-bit GPR operand. Adjust the testcase to cover both cases.
Convert VexW= to their respective VexW* on lines touched anyway.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b22ea5cdb5..5ba026e429 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Exlucde !vexw insns
+ alongside !norex64 ones.
+ * testsuite/gas/i386/x86-64-avx512bw.s: Test VPEXTR* and VPINSR*
+ with both 32- and 64-bit GPR operands.
+ * testsuite/gas/i386/x86-64-avx512f.s: Test VEXTRACTPS with both
+ 32- and 64-bit GPR operands.
+ * testsuite/gas/i386/x86-64-avx512bw-intel.d,
+ testsuite/gas/i386/x86-64-avx512bw.d,
+ testsuite/gas/i386/x86-64-avx512f-intel.d,
+ testsuite/gas/i386/x86-64-avx512f.d: Adjust expectations.
+
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Drop use of rex64.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 9a26a1df64..c5858f4c53 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6667,6 +6667,7 @@ process_suffix (void)
if (i.suffix == QWORD_MNEM_SUFFIX
&& flag_code == CODE_64BIT
&& !i.tm.opcode_modifier.norex64
+ && !i.tm.opcode_modifier.vexw
/* Special case for xchg %rax,%rax. It is NOP and doesn't
need rex64. */
&& ! (i.operands == 2
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bw-intel.d
index a589d51776..530db0e2d4 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-intel.d
@@ -229,9 +229,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 00 20 00 00[ ]*vpblendmw zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 72 80[ ]*vpblendmw zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 c0 df ff ff[ ]*vpblendmw zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb rax,xmm29,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb rax,xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 ab[ ]*vpextrb eax,xmm29,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 7b[ ]*vpextrb eax,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 7d 08 14 e8 7b[ ]*vpextrb r8d,xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 29 7b[ ]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 23 7d 08 14 ac f0 23 01 00 00 7b[ ]*vpextrb BYTE PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 6a 7f 7b[ ]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -244,9 +244,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa 00 01 00 00 7b[ ]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 6a 80 7b[ ]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa fe fe ff ff 7b[ ]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw rax,xmm30,0xab
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw rax,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 ab[ ]*vpextrw eax,xmm30,0xab
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 7b[ ]*vpextrw eax,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 11 7d 08 c5 c6 7b[ ]*vpextrw r8d,xmm30,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,eax,0xab
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,eax,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,ebp,0x7b
@@ -1076,9 +1076,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 00 20 00 00[ ]*vpblendmw zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 72 80[ ]*vpblendmw zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 c0 df ff ff[ ]*vpblendmw zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb rax,xmm29,0xab
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb rax,xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb r8,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 ab[ ]*vpextrb eax,xmm29,0xab
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 7b[ ]*vpextrb eax,xmm29,0x7b
+[ ]*[a-f0-9]+:[ ]*62 43 7d 08 14 e8 7b[ ]*vpextrb r8d,xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 29 7b[ ]*vpextrb BYTE PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 23 7d 08 14 ac f0 34 12 00 00 7b[ ]*vpextrb BYTE PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 6a 7f 7b[ ]*vpextrb BYTE PTR \[rdx\+0x7f\],xmm29,0x7b
@@ -1091,9 +1091,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa 00 01 00 00 7b[ ]*vpextrw WORD PTR \[rdx\+0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 6a 80 7b[ ]*vpextrw WORD PTR \[rdx-0x100\],xmm29,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa fe fe ff ff 7b[ ]*vpextrw WORD PTR \[rdx-0x102\],xmm29,0x7b
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw rax,xmm30,0xab
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw rax,xmm30,0x7b
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw r8,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 ab[ ]*vpextrw eax,xmm30,0xab
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 7b[ ]*vpextrw eax,xmm30,0x7b
+[ ]*[a-f0-9]+:[ ]*62 11 7d 08 c5 c6 7b[ ]*vpextrw r8d,xmm30,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 ab[ ]*vpinsrb xmm30,xmm29,eax,0xab
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 7b[ ]*vpinsrb xmm30,xmm29,eax,0x7b
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f5 7b[ ]*vpinsrb xmm30,xmm29,ebp,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw.d b/gas/testsuite/gas/i386/x86-64-avx512bw.d
index bef54f70e3..ee3385a95a 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw.d
@@ -229,9 +229,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 00 20 00 00[ ]*vpblendmw 0x2000\(%rdx\),%zmm29,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 72 80[ ]*vpblendmw -0x2000\(%rdx\),%zmm29,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 c0 df ff ff[ ]*vpblendmw -0x2040\(%rdx\),%zmm29,%zmm30
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 43 7d 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 29 7b[ ]*vpextrb \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 23 7d 08 14 ac f0 23 01 00 00 7b[ ]*vpextrb \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 6a 7f 7b[ ]*vpextrb \$0x7b,%xmm29,0x7f\(%rdx\)
@@ -244,9 +244,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa 00 01 00 00 7b[ ]*vpextrw \$0x7b,%xmm29,0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 6a 80 7b[ ]*vpextrw \$0x7b,%xmm29,-0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa fe fe ff ff 7b[ ]*vpextrw \$0x7b,%xmm29,-0x102\(%rdx\)
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 11 7d 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 ab[ ]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 7b[ ]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f5 7b[ ]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
@@ -1076,9 +1076,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 00 20 00 00[ ]*vpblendmw 0x2000\(%rdx\),%zmm29,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 72 80[ ]*vpblendmw -0x2000\(%rdx\),%zmm29,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 95 40 66 b2 c0 df ff ff[ ]*vpblendmw -0x2040\(%rdx\),%zmm29,%zmm30
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 63 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+:[ ]*62 43 fd 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 ab[ ]*vpextrb \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+:[ ]*62 43 7d 08 14 e8 7b[ ]*vpextrb \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 29 7b[ ]*vpextrb \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 23 7d 08 14 ac f0 34 12 00 00 7b[ ]*vpextrb \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 14 6a 7f 7b[ ]*vpextrb \$0x7b,%xmm29,0x7f\(%rdx\)
@@ -1091,9 +1091,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa 00 01 00 00 7b[ ]*vpextrw \$0x7b,%xmm29,0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 6a 80 7b[ ]*vpextrw \$0x7b,%xmm29,-0x100\(%rdx\)
[ ]*[a-f0-9]+:[ ]*62 63 7d 08 15 aa fe fe ff ff 7b[ ]*vpextrw \$0x7b,%xmm29,-0x102\(%rdx\)
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%rax
-[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 ab[ ]*vpextrw \$0xab,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 91 7d 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%eax
+[ ]*[a-f0-9]+:[ ]*62 11 7d 08 c5 c6 7b[ ]*vpextrw \$0x7b,%xmm30,%r8d
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 ab[ ]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f0 7b[ ]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
[ ]*[a-f0-9]+:[ ]*62 63 15 00 20 f5 7b[ ]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw.s b/gas/testsuite/gas/i386/x86-64-avx512bw.s
index 5875230173..d04ddfb68d 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw.s
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw.s
@@ -223,7 +223,7 @@ _start:
vpblendmw 8192(%rdx), %zmm29, %zmm30 # AVX512BW
vpblendmw -8192(%rdx), %zmm29, %zmm30 # AVX512BW Disp8
vpblendmw -8256(%rdx), %zmm29, %zmm30 # AVX512BW
- vpextrb $0xab, %xmm29, %rax # AVX512BW
+ vpextrb $0xab, %xmm29, %eax # AVX512BW
vpextrb $123, %xmm29, %rax # AVX512BW
vpextrb $123, %xmm29, %r8 # AVX512BW
vpextrb $123, %xmm29, (%rcx) # AVX512BW
@@ -238,13 +238,13 @@ _start:
vpextrw $123, %xmm29, 256(%rdx) # AVX512BW
vpextrw $123, %xmm29, -256(%rdx) # AVX512BW Disp8
vpextrw $123, %xmm29, -258(%rdx) # AVX512BW
- vpextrw $0xab, %xmm30, %rax # AVX512BW
+ vpextrw $0xab, %xmm30, %eax # AVX512BW
vpextrw $123, %xmm30, %rax # AVX512BW
vpextrw $123, %xmm30, %r8 # AVX512BW
vpinsrb $0xab, %eax, %xmm29, %xmm30 # AVX512BW
- vpinsrb $123, %eax, %xmm29, %xmm30 # AVX512BW
+ vpinsrb $123, %rax, %xmm29, %xmm30 # AVX512BW
vpinsrb $123, %ebp, %xmm29, %xmm30 # AVX512BW
- vpinsrb $123, %r13d, %xmm29, %xmm30 # AVX512BW
+ vpinsrb $123, %r13, %xmm29, %xmm30 # AVX512BW
vpinsrb $123, (%rcx), %xmm29, %xmm30 # AVX512BW
vpinsrb $123, 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512BW
vpinsrb $123, 127(%rdx), %xmm29, %xmm30 # AVX512BW Disp8
@@ -252,9 +252,9 @@ _start:
vpinsrb $123, -128(%rdx), %xmm29, %xmm30 # AVX512BW Disp8
vpinsrb $123, -129(%rdx), %xmm29, %xmm30 # AVX512BW
vpinsrw $0xab, %eax, %xmm29, %xmm30 # AVX512BW
- vpinsrw $123, %eax, %xmm29, %xmm30 # AVX512BW
+ vpinsrw $123, %rax, %xmm29, %xmm30 # AVX512BW
vpinsrw $123, %ebp, %xmm29, %xmm30 # AVX512BW
- vpinsrw $123, %r13d, %xmm29, %xmm30 # AVX512BW
+ vpinsrw $123, %r13, %xmm29, %xmm30 # AVX512BW
vpinsrw $123, (%rcx), %xmm29, %xmm30 # AVX512BW
vpinsrw $123, 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512BW
vpinsrw $123, 254(%rdx), %xmm29, %xmm30 # AVX512BW Disp8
@@ -1072,7 +1072,7 @@ _start:
vpblendmw zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512BW
vpblendmw zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512BW Disp8
vpblendmw zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512BW
- vpextrb rax, xmm29, 0xab # AVX512BW
+ vpextrb eax, xmm29, 0xab # AVX512BW
vpextrb rax, xmm29, 123 # AVX512BW
vpextrb r8, xmm29, 123 # AVX512BW
vpextrb BYTE PTR [rcx], xmm29, 123 # AVX512BW
@@ -1087,13 +1087,13 @@ _start:
vpextrw WORD PTR [rdx+256], xmm29, 123 # AVX512BW
vpextrw WORD PTR [rdx-256], xmm29, 123 # AVX512BW Disp8
vpextrw WORD PTR [rdx-258], xmm29, 123 # AVX512BW
- vpextrw rax, xmm30, 0xab # AVX512BW
+ vpextrw eax, xmm30, 0xab # AVX512BW
vpextrw rax, xmm30, 123 # AVX512BW
vpextrw r8, xmm30, 123 # AVX512BW
vpinsrb xmm30, xmm29, eax, 0xab # AVX512BW
- vpinsrb xmm30, xmm29, eax, 123 # AVX512BW
+ vpinsrb xmm30, xmm29, rax, 123 # AVX512BW
vpinsrb xmm30, xmm29, ebp, 123 # AVX512BW
- vpinsrb xmm30, xmm29, r13d, 123 # AVX512BW
+ vpinsrb xmm30, xmm29, r13, 123 # AVX512BW
vpinsrb xmm30, xmm29, BYTE PTR [rcx], 123 # AVX512BW
vpinsrb xmm30, xmm29, BYTE PTR [rax+r14*8+0x1234], 123 # AVX512BW
vpinsrb xmm30, xmm29, BYTE PTR [rdx+127], 123 # AVX512BW Disp8
@@ -1101,9 +1101,9 @@ _start:
vpinsrb xmm30, xmm29, BYTE PTR [rdx-128], 123 # AVX512BW Disp8
vpinsrb xmm30, xmm29, BYTE PTR [rdx-129], 123 # AVX512BW
vpinsrw xmm30, xmm29, eax, 0xab # AVX512BW
- vpinsrw xmm30, xmm29, eax, 123 # AVX512BW
+ vpinsrw xmm30, xmm29, rax, 123 # AVX512BW
vpinsrw xmm30, xmm29, ebp, 123 # AVX512BW
- vpinsrw xmm30, xmm29, r13d, 123 # AVX512BW
+ vpinsrw xmm30, xmm29, r13, 123 # AVX512BW
vpinsrw xmm30, xmm29, WORD PTR [rcx], 123 # AVX512BW
vpinsrw xmm30, xmm29, WORD PTR [rax+r14*8+0x1234], 123 # AVX512BW
vpinsrw xmm30, xmm29, WORD PTR [rdx+254], 123 # AVX512BW Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f-intel.d
index ff2a3d103b..867be88826 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512f-intel.d
@@ -2709,9 +2709,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee ab vextracti64x4 ymm30\{k7\},zmm29,0xab
[ ]*[a-f0-9]+: 62 03 fd cf 3b ee ab vextracti64x4 ymm30\{k7\}\{z\},zmm29,0xab
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee 7b vextracti64x4 ymm30\{k7\},zmm29,0x7b
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 ab vextractps eax,xmm29,0xab
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 7b vextractps eax,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 43 7d 08 17 e8 7b vextractps r8d,xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 7d 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 23 7d 08 17 ac f0 23 01 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 7d 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
@@ -9730,9 +9730,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee ab vextracti64x4 ymm30\{k7\},zmm29,0xab
[ ]*[a-f0-9]+: 62 03 fd cf 3b ee ab vextracti64x4 ymm30\{k7\}\{z\},zmm29,0xab
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee 7b vextracti64x4 ymm30\{k7\},zmm29,0x7b
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 ab vextractps eax,xmm29,0xab
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 7b vextractps eax,xmm29,0x7b
+[ ]*[a-f0-9]+: 62 43 7d 08 17 e8 7b vextractps r8d,xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 7d 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 23 7d 08 17 ac f0 34 12 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
[ ]*[a-f0-9]+: 62 63 7d 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.d b/gas/testsuite/gas/i386/x86-64-avx512f.d
index 652bfc6ab1..9ca2c1eded 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512f.d
@@ -2708,9 +2708,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee ab vextracti64x4 \$0xab,%zmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+: 62 03 fd cf 3b ee ab vextracti64x4 \$0xab,%zmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee 7b vextracti64x4 \$0x7b,%zmm29,%ymm30\{%k7\}
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 ab vextractps \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 7b vextractps \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 43 7d 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+: 62 63 7d 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+: 62 23 7d 08 17 ac f0 23 01 00 00 7b vextractps \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
[ ]*[a-f0-9]+: 62 63 7d 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
@@ -9729,9 +9729,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee ab vextracti64x4 \$0xab,%zmm29,%ymm30\{%k7\}
[ ]*[a-f0-9]+: 62 03 fd cf 3b ee ab vextracti64x4 \$0xab,%zmm29,%ymm30\{%k7\}\{z\}
[ ]*[a-f0-9]+: 62 03 fd 4f 3b ee 7b vextracti64x4 \$0x7b,%zmm29,%ymm30\{%k7\}
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
-[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 ab vextractps \$0xab,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 63 7d 08 17 e8 7b vextractps \$0x7b,%xmm29,%eax
+[ ]*[a-f0-9]+: 62 43 7d 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8d
[ ]*[a-f0-9]+: 62 63 7d 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
[ ]*[a-f0-9]+: 62 23 7d 08 17 ac f0 34 12 00 00 7b vextractps \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
[ ]*[a-f0-9]+: 62 63 7d 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.s b/gas/testsuite/gas/i386/x86-64-avx512f.s
index 31a009008a..f259525b14 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f.s
+++ b/gas/testsuite/gas/i386/x86-64-avx512f.s
@@ -2953,7 +2953,7 @@ _start:
vextracti64x4 $0xab, %zmm29, %ymm30{%k7}{z} # AVX512F
vextracti64x4 $123, %zmm29, %ymm30{%k7} # AVX512F
- vextractps $0xab, %xmm29, %rax # AVX512F
+ vextractps $0xab, %xmm29, %eax # AVX512F
vextractps $123, %xmm29, %rax # AVX512F
vextractps $123, %xmm29, %r8 # AVX512F
vextractps $123, %xmm29, (%rcx) # AVX512F
@@ -10611,7 +10611,7 @@ _start:
vextracti64x4 ymm30{k7}{z}, zmm29, 0xab # AVX512F
vextracti64x4 ymm30{k7}, zmm29, 123 # AVX512F
- vextractps rax, xmm29, 0xab # AVX512F
+ vextractps eax, xmm29, 0xab # AVX512F
vextractps rax, xmm29, 123 # AVX512F
vextractps r8, xmm29, 123 # AVX512F
vextractps DWORD PTR [rcx], xmm29, 123 # AVX512F
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7f30463897..487e3df642 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2020-03-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
+ (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
+ pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
+ VexW0 on SSE2AVX variants.
+ (vmovq): Drop NoRex64 from XMM/XMM variants.
+ (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
+ vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
+ applicable use VexW0.
+ * i386-tbl.h: Re-generate.
+
2020-03-06 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Remove Rex64 field.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index ee80d28e69..0b3d9dfc1c 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1026,8 +1026,8 @@ movq, 2, 0xa1, None, 1, Cpu64, D|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
movq, 2, 0x89, None, 1, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixOk=3, { Reg64, Reg64|Unspecified|Qword|BaseIndex }
movq, 2, 0xc7, 0x0, 1, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixOk=3|Optimize, { Imm32S, Reg64|Qword|Unspecified|BaseIndex }
movq, 2, 0xb8, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
-movq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
+movq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM }
movq, 2, 0xf30f7e, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM }
movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM }
@@ -1293,7 +1293,7 @@ movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu
movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
movlps, 2, 0xf12, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
+movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg32|Reg64 }
movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
@@ -1317,14 +1317,14 @@ pavgb, 2, 0x660fe0, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q
pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
-pextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
-pextrw, 3, 0x6615, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
+pextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
+pextrw, 3, 0x6615, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, RegMem|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, RegMMX, Reg32|Reg64 }
-pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
+pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
@@ -1342,7 +1342,7 @@ pminsw, 2, 0xfea, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No
pminub, 2, 0x66da, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminub, 2, 0x660fda, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
pminub, 2, 0xfda, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
-pmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
+pmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg32|Reg64 }
pmovmskb, 2, 0x660fd7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
pmovmskb, 2, 0xfd7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { RegMMX, Reg32|Reg64 }
pmulhuw, 2, 0x66e4, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
@@ -1464,7 +1464,7 @@ movhpd, 2, 0x660f16, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu
movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
movlpd, 2, 0x660f12, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
+movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg32|Reg64 }
movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
movntpd, 2, 0x660f2b, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
@@ -1695,7 +1695,7 @@ dppd, 3, 0x660f3a41, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
dpps, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
dpps, 3, 0x660f3a40, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-extractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg64 }
+extractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64 }
extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1|Cpu64, RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64 }
insertps, 3, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -1714,7 +1714,7 @@ pblendw, 3, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|No_b
pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqq, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpeqq, 2, 0x660f3829, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
-pextrb, 3, 0x6614, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
+pextrb, 3, 0x6614, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, RegMem|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
@@ -1724,7 +1724,7 @@ pextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|VexW1|No_bSuf|No
pextrq, 3, 0x660f3a16, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex }
phminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
phminposuw, 2, 0x660f3841, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
-pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
+pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
@@ -1782,7 +1782,7 @@ roundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|No_bSuf|No_wSu
roundpd, 3, 0x660f3a09, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
roundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
roundps, 3, 0x660f3a08, None, 3, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-roundsd, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+roundsd, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
roundsd, 3, 0x660f3a0b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
roundss, 3, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
roundss, 3, 0x660f3a0a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -2055,7 +2055,7 @@ vdppd, 4, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|No_bSu
vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-vextractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64 }
+vextractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64 }
vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -2100,14 +2100,14 @@ vmovlpd, 3, 0x6612, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|Igno
vmovlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
vmovlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vmovlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
-vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM|RegYMM, Reg32|Reg64 }
-vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM|RegYMM, Reg32|Reg64 }
+vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
+vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }
vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
-vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
+vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
@@ -2165,12 +2165,12 @@ vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|Ch
vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vpextrb, 3, 0x6614, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
+vpextrb, 3, 0x6614, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex }
-vpextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
-vpextrw, 3, 0x6615, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
+vpextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
+vpextrw, 3, 0x6615, None, 1, CpuAVX, RegMem|Vex|VexOpcode=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphaddsw, 3, 0x6603, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -2179,11 +2179,11 @@ vphminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|No_bSuf|No
vphsubd, 3, 0x6606, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphsubsw, 3, 0x6607, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vphsubw, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
+vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
vpinsrd, 4, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
+vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -2199,7 +2199,7 @@ vpminsw, 3, 0x66ea, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No
vpminub, 3, 0x66da, None, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminud, 3, 0x663b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpminuw, 3, 0x663a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vpmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
+vpmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM, Reg32|Reg64 }
vpmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -2268,7 +2268,7 @@ vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_b
vrcpss, 3, 0xf353, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vroundsd, 4, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vroundsd, 4, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vroundss, 4, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vrsqrtss, 3, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -2350,7 +2350,7 @@ vpminsw, 3, 0x66ea, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG
vpminub, 3, 0x66da, None, 1, CpuAVX2, Modrm|C|Vex=2|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminud, 3, 0x663b, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpminuw, 3, 0x663a, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
-vpmovmskb, 2, 0x66d7, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
+vpmovmskb, 2, 0x66d7, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegYMM, Reg32|Reg64 }
vpmovsxbd, 2, 0x6621, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovsxbq, 2, 0x6622, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovsxbw, 2, 0x6620, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 012f367451..74bb964cac 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -9052,7 +9052,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
0, 1, 0, 0, 1, 0 } },
@@ -9066,7 +9066,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } },
@@ -12682,7 +12682,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } },
@@ -13018,7 +13018,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -13034,7 +13034,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -13130,7 +13130,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -13394,7 +13394,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } },
@@ -15044,7 +15044,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } },
@@ -17862,7 +17862,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 2, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -18150,7 +18150,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 2, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -18306,7 +18306,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -19142,7 +19142,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 1, 1, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 1, 2, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -28906,7 +28906,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 2, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -30062,7 +30062,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } },
@@ -30076,7 +30076,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } },
@@ -30216,7 +30216,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
0, 1, 0, 0, 1, 0 } },
@@ -30230,7 +30230,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } },
@@ -32510,7 +32510,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 2, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -32638,7 +32638,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -32654,7 +32654,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 2, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -32940,7 +32940,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 3, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 2, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -33084,7 +33084,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
@@ -33828,7 +33828,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } },
@@ -33842,7 +33842,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } },
@@ -37268,7 +37268,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 1, 3, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 3, 2, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
next reply other threads:[~2020-03-16 18:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-16 18:49 gdb-buildbot [this message]
2020-03-16 18:49 ` Failures on Fedora-x86_64-cc-with-index, branch master gdb-buildbot
2020-03-16 18:58 ` Failures on Fedora-i686, " gdb-buildbot
2020-03-16 19:44 ` Failures on Fedora-x86_64-m64, " gdb-buildbot
2020-03-16 20:01 ` Failures on Fedora-x86_64-native-extended-gdbserver-m32, " gdb-buildbot
2020-03-16 20:45 ` Failures on Fedora-x86_64-native-extended-gdbserver-m64, " gdb-buildbot
2020-03-18 22:05 ` Failures on Ubuntu-Aarch64-native-extended-gdbserver-m64, " gdb-buildbot
2020-03-18 23:27 ` Failures on Fedora-x86_64-native-gdbserver-m64, " gdb-buildbot
2020-03-18 23:54 ` Failures on Ubuntu-Aarch64-native-gdbserver-m64, " gdb-buildbot
2020-03-19 15:35 ` Failures on Fedora-x86_64-native-gdbserver-m32, " gdb-buildbot
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