From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 64860 invoked by alias); 3 May 2018 21:34:43 -0000 Mailing-List: contact gdb-testers-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-testers-owner@sourceware.org Received: (qmail 64843 invoked by uid 89); 3 May 2018 21:34:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: kwanyin.sergiodj.net Received: from kwanyin.sergiodj.net (HELO kwanyin.sergiodj.net) (158.69.185.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 03 May 2018 21:34:41 +0000 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [binutils-gdb] gdb/testsuite: Filter out some registers for riscv From: sergiodj+buildbot@sergiodj.net To: gdb-testers@sourceware.org Message-Id: <9b0797e268d96e8b46c328792aec3d6289585aa2@gdb-build> Date: Thu, 03 May 2018 21:34:00 -0000 X-SW-Source: 2018-q2/txt/msg03170.txt.bz2 *** TEST RESULTS FOR COMMIT 9b0797e268d96e8b46c328792aec3d6289585aa2 *** Author: Andrew Burgess Branch: master Commit: 9b0797e268d96e8b46c328792aec3d6289585aa2 gdb/testsuite: Filter out some registers for riscv On riscv the cycle counter, and instructions retired counter CSRs are read only, this causes problems in the gdb.base/callfuncs.exp test, as the values in these CSRs change after an inferior call, the check that no target registers have been modified then fails. Luckily the test already has a mechanism in place for filtering out registers that are modified (and can't be restored) by an inferior call, so this commit adds the problem registers into this list for riscv. In the future we may end up needing to filter out more CSRs, but right now, for the targets I have access too, these are the only ones causing problems. gdb/testsuite/ChangeLog: * gdb.base/callfuncs.exp (fetch_all_registers): Add riscv register filter pattern.