From: John Baldwin <jhb@FreeBSD.org>
To: James Becker <james.becker@crossfire-tech.com>, gdb@sourceware.org
Subject: Re: gdb for Riscv, single stepping issue
Date: Tue, 28 Jun 2022 08:52:20 -0700 [thread overview]
Message-ID: <069ae440-5fc5-b853-e415-e9643e6d8144@FreeBSD.org> (raw)
In-Reply-To: <a6adfd76-c34c-c150-1829-49277fc9d3da@crossfire-tech.com>
On 6/27/22 1:40 PM, James Becker wrote:
> Hello,
>
> I have a RISCV-EL2 core running in a Nexys A7 FPGA board.
>
> I have openocd for riscv running over jtag with a connection by
> riscv-gdb to the openocd instance at port 3333.
>
> Everything works fine, stepping, break points, load, view memory.
>
> But I have one issue: Some of the memory in my design is 4 byte
> aligned. Its designed for fast instruction fetch, its known as ICCM.
>
> When I have code running in that memory, gdb still works fine for
> breakpoints, but it will not single step.
>
> Looking at the openocd debug files, it appears that gdb is attempting to
> do a 2 byte read as a part of the single stepping procedure.
>
> Since my memory does not support 2 byte reads or writes, this fails.
>
> Is there some way that gdb can be configured to not do any 2-byte word
> reads or writes during single stepping? I can't seem to find any.
Hmm, setting breakpoints tries to read 1 byte at a time unless you have
disabled compressed breakpoints. It looks like as a local hack you could
change use-compressed-breakpoints to just read 4 bytes rather than 2
initially? Perhaps this is upstreamable if you make it read 4 bytes if
the target address is 4 byte aligned and only fall back to reading 2 bytes
if it isn't?
--
John Baldwin
next prev parent reply other threads:[~2022-06-28 15:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 20:40 James Becker
2022-06-28 15:52 ` John Baldwin [this message]
2022-06-29 9:34 ` Pedro Alves
2022-06-29 16:27 ` James Becker
2022-06-29 17:54 ` John Baldwin
2022-06-30 9:40 ` Pedro Alves
2022-07-03 3:58 ` James Becker
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