From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25184 invoked by alias); 15 Jul 2003 07:30:40 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 25177 invoked from network); 15 Jul 2003 07:30:40 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sources.redhat.com with SMTP; 15 Jul 2003 07:30:40 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.11.6/8.11.6) with ESMTP id h6F7UdH06746 for ; Tue, 15 Jul 2003 03:30:39 -0400 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [172.16.52.156]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h6F7UdI05829 for ; Tue, 15 Jul 2003 03:30:39 -0400 Received: from localhost.localdomain (vpn50-28.rdu.redhat.com [172.16.50.28]) by pobox.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h6F7Udb00855 for ; Tue, 15 Jul 2003 03:30:39 -0400 Received: (from kev@localhost) by localhost.localdomain (8.11.6/8.11.6) id h6F7UX003809 for gdb@sources.redhat.com; Tue, 15 Jul 2003 00:30:33 -0700 Date: Tue, 15 Jul 2003 07:30:00 -0000 From: Kevin Buettner Message-Id: <1030715073033.ZM3808@localhost.localdomain> To: gdb@sources.redhat.com Subject: Enable SSE registers by default? MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2003-07/txt/msg00159.txt.bz2 The function i386_gdbarch_init() in i386-tdep.c contains the following comment/code: /* The i386 default settings don't include the SSE registers. FIXME: kettenis/20020614: They do include the FPU registers for now, which probably is not quite right. */ tdep->num_xmm_regs = 0; I would like to see the SSE registers enabled by default, or, if that proves to be undesirable for some reason, we should have some way of enabling them for targets which support them. (Note that i386-linux-tdep.c enables SSE register support unconditionally.) The only drawback that I'm aware of with enabling them by default is that they'll be displayed in ``info all-registers'' even for devices which don't have these registers. But, I think they'll always show up as zero (for remote targets anyway), which is the same behavior that I'd expect to see for FPU-less cores. I think this is the reason behind Mark's FIXME comment. Is anyone aware of any other drawbacks? Kevin