From: Daniel Jacobowitz <drow@mvista.com>
To: gdb@sources.redhat.com
Subject: RFC: Unpredictable register set operations
Date: Tue, 15 Jul 2003 22:09:00 -0000 [thread overview]
Message-ID: <20030715220923.GA30513@nevyn.them.org> (raw)
I'm sure this has come up before, but I couldn't find a discussion anywhere
so I'll just have to ask again...
Consider PowerPC and the $ps register (MSR). When debugging a kernel or
embedded application, GDB has pretty complete control (?) over this
register. In GNU/Linux userspace, however, only two bits of it can be set.
The rest are read-only.
So what happens if you "set $ps = 0"? Well, the right thing happens, but
until the next time the target stops "print $ps" will print 0. Which is not
actually the value of the $ps register.
Here's the options that I see:
- Ignore and document this.
- Refetch registers after storing them.
- Invalidate registers for lazy re-fetch after storing them.
- Add a target hook for might-be-volatile registers, and invalidate
only those registers after storing them - or don't cache them at
all.
Thoughts? Is this a problem worth fixing?
--
Daniel Jacobowitz
MontaVista Software Debian GNU/Linux Developer
next reply other threads:[~2003-07-15 22:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-15 22:09 Daniel Jacobowitz [this message]
2003-07-15 22:27 ` Kevin Buettner
2003-07-15 22:29 ` Doug Evans
2003-07-16 2:46 ` Andrew Cagney
2003-07-16 3:21 ` Daniel Jacobowitz
2003-07-21 16:48 ` Daniel Jacobowitz
2003-08-05 5:13 ` Andrew Cagney
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