From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19343 invoked by alias); 7 Nov 2005 00:22:43 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 19333 invoked by uid 22791); 7 Nov 2005 00:22:41 -0000 Received: from nevyn.them.org (HELO nevyn.them.org) (66.93.172.17) by sourceware.org (qpsmtpd/0.30-dev) with ESMTP; Mon, 07 Nov 2005 00:22:41 +0000 Received: from drow by nevyn.them.org with local (Exim 4.54) id 1EYumU-0005OB-K9; Sun, 06 Nov 2005 19:22:38 -0500 Date: Mon, 07 Nov 2005 00:22:00 -0000 From: Daniel Jacobowitz To: Chris Johns Cc: gdb@sources.redhat.com Subject: Re: selecting a processor variant with gdbarch. Message-ID: <20051107002238.GA20613@nevyn.them.org> Mail-Followup-To: Chris Johns , gdb@sources.redhat.com References: <4365D115.9070406@contemporary.net.au> <20051031141943.GC25504@nevyn.them.org> <436730E3.9040700@contemporary.net.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <436730E3.9040700@contemporary.net.au> User-Agent: Mutt/1.5.8i X-SW-Source: 2005-11/txt/msg00131.txt.bz2 On Tue, Nov 01, 2005 at 08:09:55PM +1100, Chris Johns wrote: > Daniel Jacobowitz wrote: > >On Mon, Oct 31, 2005 at 07:08:53PM +1100, Chris Johns wrote: > > > >>Hello, > >> > >>What is the preferred way to have gdbarch select a specific processor > >>variant ? > > > > > >Can you be more specific about what you want? > > > > On the Coldfire we have a growing number of processors with a few > different cores each running the same code, yet with register sets that > vary in different ways. Wait, are you talking about multiple slightly heterogeneous cores at the same time, or across different implementations? I'm not sure from the above. > When using BDM with a Coldfire you need to get at some of the processor > specific registers to access memory controllers to enable RAM to > download a program. > > We can teach a BDM target ops how to detect various processors and make > the selection. Getting gdbarch to handle the change is what I would like > to understand. Take a look at the code on csl-arm-20050325-branch for more information about this, specifically arm-tdep.c:arm_update_architecture. That's not what it will look like in GDB HEAD once it is implemented there; but you can find some more about the topic in the gdb@ list archives from early this year. > I have played around with changing the register names and types but > regcache proved a hurdle. It sets up the cache once during > initialisation. If I could make a a call to get regcache to > re-initialise this hurdle could be overcome. See the bottom of arm_update_architecture for more. The trick is to switch to a "new" gdbarch. -- Daniel Jacobowitz CodeSourcery, LLC