From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 44265 invoked by alias); 12 Jun 2019 17:29:03 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 44257 invoked by uid 89); 12 Jun 2019 17:29:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=1.8 required=5.0 tests=AWL,BAYES_00,SPAM_BODY1,SPF_PASS autolearn=no version=3.3.1 spammy=5.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Jun 2019 17:29:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7801428; Wed, 12 Jun 2019 10:29:00 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E5FA3F246; Wed, 12 Jun 2019 10:28:59 -0700 (PDT) Date: Wed, 12 Jun 2019 17:29:00 -0000 From: Will Deacon To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, gdb@sourceware.org, Alex =?iso-8859-1?Q?Benn=E9e?= , Julien Grall , Catalin Marinas , Peter Maydell , Zhang Lei , Alan Hayward Subject: Re: [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions Message-ID: <20190612172853.GA27039@fuggles.cambridge.arm.com> References: <1560355234-25516-1-git-send-email-Dave.Martin@arm.com> <1560355234-25516-2-git-send-email-Dave.Martin@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1560355234-25516-2-git-send-email-Dave.Martin@arm.com> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-SW-Source: 2019-06/txt/msg00027.txt.bz2 On Wed, Jun 12, 2019 at 05:00:32PM +0100, Dave Martin wrote: > The in-memory representation of SVE and FPSIMD registers is > different: the FPSIMD V-registers are stored as single 128-bit > host-endian values, whereas SVE registers are stored in an > endianness-invariant byte order. > > This means that the two representations differ when running on a > big-endian host. But we blindly copy data from one representation > to another when converting between the two, resulting in the > register contents being unintentionally byteswapped in certain > situations. Currently this can be triggered by the first SVE > instruction after a syscall, for example (though the potential > trigger points may vary in future). > > So, fix the conversion functions fpsimd_to_sve(), sve_to_fpsimd() > and sve_sync_from_fpsimd_zeropad() to swab where appropriate. > > There is no common swahl128() or swab128() that we could use here. > Maybe it would be worth making this generic, but for now add a > simple local hack. > > Since the byte order differences are exposed in ABI, also clarify > the docuentation. > > Fixes: bc0ee4760364 ("arm64/sve: Core task context handling") > Fixes: 8cd969d28fd2 ("arm64/sve: Signal handling support") > Fixes: 43d4da2c45b2 ("arm64/sve: ptrace and ELF coredump support") > Signed-off-by: Dave Martin Thanks, Dave. I've picked this one up and pushed it out to our fixes branch for 5.2. I assume Catalin will take the other two for 5.3. It's probably worth proposing some generic 128-bit swab functions too, in case there's any interest (in which case we could drop our local implementation later on). Cheers, Will