From: Andrew Cagney <ac131313@redhat.com>
To: Daniel Jacobowitz <drow@mvista.com>
Cc: gdb@sources.redhat.com
Subject: Re: RFC: Unpredictable register set operations
Date: Tue, 05 Aug 2003 05:13:00 -0000 [thread overview]
Message-ID: <3F2F3D0C.2070607@redhat.com> (raw)
In-Reply-To: <20030721164850.GA7494@nevyn.them.org>
> This is a straight bug. The register cache should be marked as invalid
>> > after the store. What puzzles me is why store.exp doesn't tickle this,
>> > or is this a hangover from lval_register vs lval_reg_frame_relative?
>
>>
>> Where's the invalidation supposed to happen presently? Perhaps I need
>> to retest.
>
>
> I don't know if we're talking about the same thing, but this definitely
> doesn't happen now. I believe we invalidate the frame cache, not
> the current regcache... try it, for example on a remote ARM target:
>
> set debug remote 1
> info registers
> [see the g packet]
> set $r0 = 2
> [see the G packet]
> info registers
> [from the cache, no packets on the wire]
Sounds like it never did. It needs to though (the missing function
target_changed). After a write, the target state should be flushed.
Andrew
prev parent reply other threads:[~2003-08-05 5:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-15 22:09 Daniel Jacobowitz
2003-07-15 22:27 ` Kevin Buettner
2003-07-15 22:29 ` Doug Evans
2003-07-16 2:46 ` Andrew Cagney
2003-07-16 3:21 ` Daniel Jacobowitz
2003-07-21 16:48 ` Daniel Jacobowitz
2003-08-05 5:13 ` Andrew Cagney [this message]
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