From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from nx235.node02.secure-mailgate.com (nx235.node02.secure-mailgate.com [192.162.87.235]) by sourceware.org (Postfix) with ESMTPS id 422A9385781A for ; Mon, 22 Mar 2021 15:13:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 422A9385781A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=trande.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=zied.guermazi@trande.de Received: from host202.checkdomain.de ([185.137.168.148]) by node02.secure-mailgate.com with esmtps (TLSv1.2:AES128-GCM-SHA256:128) (Exim 4.92) (envelope-from ) id 1lOMFA-009gxx-Dm; Mon, 22 Mar 2021 16:13:25 +0100 X-SecureMailgate-Identity: host202.checkdomain.de Received: from [192.168.178.48] (x4dbd4c14.dyn.telefonica.de [77.189.76.20]) (Authenticated sender: zied.guermazi@trande.de) by host202.checkdomain.de (Postfix) with ESMTPSA id E10C9358081; Mon, 22 Mar 2021 16:13:21 +0100 (CET) X-SecureMailgate-Identity: host202.checkdomain.de Subject: Re: flag to know that we are compiling GDB for an arm target To: Simon Marchi , "Metzger, Markus T" , "gdb@sourceware.org" References: <2a6681a1-f672-0ae9-3aa7-8001330a8661@trande.de> <73d48246-983d-5b0b-be40-dee0423daf43@polymtl.ca> <4d77ba55-5ca6-4b44-2cc7-ecbb37ff26b6@trande.de> <0f6dc0a0-ad67-5247-34a1-8b22f41087ca@polymtl.ca> <57c29c80-57e1-8c93-592e-f2cb11ff4ae1@trande.de> <2ab101e8-5e75-717e-9d87-11d1c4aa0f91@trande.de> <8c00ecf0-ca44-0729-b576-8347078dc324@polymtl.ca> From: Zied Guermazi Message-ID: <4e17a72a-76bb-8f75-c85c-ee6cc5705bd9@trande.de> Date: Mon, 22 Mar 2021 16:13:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <8c00ecf0-ca44-0729-b576-8347078dc324@polymtl.ca> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-PPP-Message-ID: <20210322151322.1348454.69665@host202.checkdomain.de> X-PPP-Vhost: trande.de X-Originating-IP: 185.137.168.148 X-SecureMailgate-Domain: host202.checkdomain.de X-SecureMailgate-Username: 185.137.168.148 Authentication-Results: secure-mailgate.com; auth=pass smtp.auth=185.137.168.148@host202.checkdomain.de X-SecureMailgate-Outgoing-Class: ham X-SecureMailgate-Outgoing-Evidence: Combined (0.15) X-Recommended-Action: accept X-Filter-ID: Pt3MvcO5N4iKaDQ5O6lkdGlMVN6RH8bjRMzItlySaT9WLQux0N3HQm8ltz8rnu+BPUtbdvnXkggZ 3YnVId/Y5jcf0yeVQAvfjHznO7+bT5xepKJyYLZISh0ScmnJxtOQL++T0fzDkcbraJCnPSgcQp91 ADy6bERTai4lQUfi0ov8b0HBt1XxwT2dNX3uS9wPcZmGlrSbXcSPbv3Gvk7oTkyC4eJXgSa0625S 60JUzdRE8BxN4qA1eT/+IFtuVb5DQp18NgnGCsx1bmdbb4szydP1+0zGDBEL130M02qMC0xQQhQ3 cXtTqZg6zYv+9efs/3vpuC4FAH4JcvbUWkbVjlvDRwp5U4jfYMAI/BBCrWaDwIE7VKe+bqpcdCns 72R1mlXslD7dplOOl8u9l7Br8NgwkGMnnSmiQIWE0h92BVmAd9sXdiOHyQc5jb5UsXBPtIMjc0Hv rCoIShx9Egj+5Y+JGC12hEo3bceCxZ00pJHUeeKYPM7sNcCy02izXOJhm4aVlBObnVhI6K7gAuPO 44MKM78T+LcmbVApU1OtExg2rRldRnnnohbUS3YD3Jmemtj2kTuR+vfsAwCLZsSPL9ckMeF4hOay CbDJxxTX92I93SsS4aMXJmiJ2G0eb5ah5Q4VQAf9BGA/4589jmSb+rM5VcI9Z9iQLx1EhkIGnvdO B2XvjaW5uTwPc8WgwrrudZBcpDAIWdCADSwEOtnmZWoMdUyXUOAkAA03/kA2wnXIHYi/jghIJpVk vIZQze0BrE7uWy+cBHv3/b8naGjYIYu2YiRYSRoqs6XmmhhLlviLJLl3zmP4k4tgfTIxb+imN1vl 9cBTxWFG2vZmPXbe8xu1F07ZTzG5p6pYQpZ8qnXD/V3AlLsOWpVGhJKQeyhTzO+LPg7xISr2Y+Dy 8YCrK7734QDJ3HhluVo9DS81JHGO0ZkW2vkOTJT9oRh6vnQYFbpsRgVhqYxD9zNCHPi/lwc/1MdF Nf3Bg+gqisYRN4c7gqll0qssN4lx/Dun58B7nDqBzt/h+lyjaFmwbbCd48OpyKA69LF1Ge2GaGfx mfqx6SI8+0/Lb/TTMB8FF2VYA1/xx+UuuEf3h3NtOf+zHWCI6y95aUyb0ByL/85xvAwowAOZKBM6 e/bYB566DxuD5CO0yszN6JvP5bqvQPT9H/5uM2OaT1C8sNNRiDFO0DtShOH22SRgbHWq1uciMDoD 4FQ8ADxJsoknBaXqeoa4KA== X-Report-Abuse-To: spam@node04.secure-mailgate.com X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, NICE_REPLY_A, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Mar 2021 15:13:39 -0000 hi On 22.03.21 16:06, Simon Marchi wrote: > > On 2021-03-22 10:53 a.m., Zied Guermazi wrote: >> hi >> >> I will put different solutions together with advantages disadvantages >> >> - add a vector of registers to each instruction >> >> advantage: close to the logical model: a function is a set of instructions, an instruction changes a set of registers. >> >> disadvantage: consumes much memory (3 additional pointers, for an empty vector) >> >> - extend the instruction class >> >> advantage: targets not needing the registers are not heavily impacted >> >> disadvantages: still an additional pointer is added >> >> - Infer the ISA mode from mapping symbols >> >> advantages: no overhead in the data structure >> >> disadvantages: dwarf info are not always available. > The mapping symbols (if I understand correctly, $a and $t) are not in > the DWARF, they are ELF symbols. However, is it possible to record > execution when you don't event have and ELF file, just connect to a > target and record it? In that case, you might not even have ELF > symbols, so that's perhaps not sufficient. > > There's also the case of self-modifying or JIT-ed code, where mapping > symbols from the ELF file are of no use. So I think it's better to just > always rely on CPSR. > >> - use additional bits in btrace_insn_flag >> >> advantages: no memory overhead >> >> disadvantages: encode architecture specific info. > Since we already pay the cost of having space for flags, we might as > well use it. It sounds like a good solution for your current problem, > since there is very little info you need to keep (the execution mode). > That doesn't solve the problem for when you'll want to record data > though, a more flexible solution will be needed. > >> I will go for using additional bits (bit 1, bit 2 and bit 3) in btrace_insn_flag to encode the isa for armv7 as folowing >> >> ocsd_isa_arm as 0x02 >> >> ocsd_isa_thumb2 as 0x04 >> >> ocsd_isa_tee as 0x06 >> >> ocsd_isa_jazelle as 0x08 > Is that 0x06 really what you want, it's a OR of arm and thumb2? that is not a big issue, I can mask the flags value with 0x0E and then compare against the value of the isa (the 3bits are handled as one flag). it will be one switch case. > > Simon /Zied