From: James Becker <james.becker@crossfire-tech.com>
To: Pedro Alves <pedro@palves.net>, John Baldwin <jhb@FreeBSD.org>,
"gdb@sourceware.org" <gdb@sourceware.org>
Subject: Re: gdb for Riscv, single stepping issue
Date: Sun, 3 Jul 2022 03:58:39 +0000 [thread overview]
Message-ID: <DM5PR1201MB00604FF4B790B818CE83D963A2BF9@DM5PR1201MB0060.namprd12.prod.outlook.com> (raw)
In-Reply-To: <357a6158-6e3a-ae13-bdd6-cfb5f98fb84f@palves.net>
Hi Pedro,
I did make the change and recompiled, but I have unfortunately lost my hardware program to my client for testing.
So it will be a week or two until I can test.
Thanks for your help.
Jim
________________________________
From: Pedro Alves <pedro@palves.net>
Sent: Thursday, June 30, 2022 4:40 AM
To: John Baldwin <jhb@FreeBSD.org>; James Becker <james.becker@crossfire-tech.com>; gdb@sourceware.org <gdb@sourceware.org>
Subject: Re: gdb for Riscv, single stepping issue
Hi!
Jim, could you check whether the patch below addresses the issue for you?
I imagine it does, but it'd be good to hear just in case we're missing some
more target_read_memory calls somewhere or some such.
Pedro Alves
On 2022-06-29 18:54, John Baldwin wrote:
> On 6/29/22 2:34 AM, Pedro Alves wrote:
>> OTOH, riscv_insn::fetch_instruction uses target_read_memory to read 2 bytes,
>> so I wonder whether this is the access in question:
>>
>> /* All insns are at least 16 bits. */
>> status = target_read_memory (addr, buf, 2);
>> if (status)
>> memory_error (TARGET_XFER_E_IO, addr);
>>
>> Why is this using target_read_memory instead of target_read_code, though?
>> If it did that, then the code cache would be involved here too, papering over
>> the issue, presumably.
>>
> Yes, I had reworked my e-mail part way through and I really meant to talk about
> this code, not the breakpoint code. I agree that target_read_code is probably
> more correct in fetch_instruction and would in this case hide the odd behavior
> of the stub:
>
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 69f2123dcdb..09b2599e958 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -1661,7 +1661,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
> int instlen, status;
>
> /* All insns are at least 16 bits. */
> - status = target_read_memory (addr, buf, 2);
> + status = target_read_code (addr, buf, 2);
> if (status)
> memory_error (TARGET_XFER_E_IO, addr);
>
> @@ -1672,7 +1672,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
>
> if (instlen > 2)
> {
> - status = target_read_memory (addr + 2, buf + 2, instlen - 2);
> + status = target_read_code (addr + 2, buf + 2, instlen - 2);
> if (status)
> memory_error (TARGET_XFER_E_IO, addr + 2);
> }
>
>
prev parent reply other threads:[~2022-07-03 3:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 20:40 James Becker
2022-06-28 15:52 ` John Baldwin
2022-06-29 9:34 ` Pedro Alves
2022-06-29 16:27 ` James Becker
2022-06-29 17:54 ` John Baldwin
2022-06-30 9:40 ` Pedro Alves
2022-07-03 3:58 ` James Becker [this message]
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