From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id F0C903858C78 for ; Mon, 11 Mar 2024 10:41:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F0C903858C78 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F0C903858C78 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710153675; cv=none; b=P9MsfJMZS3vLZxvqUgZm7O4KXtI0xwWpntsPvW9JV3FOPi1hQA4y2qYUTCxAPgWDxtmR6aEYiQ/jaMRactC0xsGNVE/cXNzhDb5sqfCYk7E7krjpeVd6vIr04xtBC/X5TSOMFev/n4tZYgH9J5R4uwQ41s5qtIjDQq+vxR4SD4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710153675; c=relaxed/simple; bh=ctMNos44vRYue7USp7bF2kHMM/w1uHPYKQJyQYz5yNo=; h=DKIM-Signature:Message-ID:Date:MIME-Version:To:From:Subject; b=UVu1yIhQfrYIHX+9emc5XXzLvns/4pQ8+Ov0EROmRnhIJHfbqwXNGQgxTdu4ZSxage4BgBygq7H6cUpU2Mn3ovatLtBLD2qmiCdejuPYDgTuxd59Ljo1piZ+mSbcwzCn9QjiIWw9dnLqbiHplIUXD3ufrc+moKbUhKWR7IM5QQo= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710153673; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OpOQFWK3/C6gWxMo6CvhyKUBXkfyJrGnN7rC38owr3Q=; b=hul1Wm3PMuocCvsY3OXC5C2sVEyQdA4fS/bzdRU42jJ2Rr03YDgniPLMFXp6EJG1T+6SOS eB4n+BtOd1uAkP7Gubh/KR70QvLE/iX4DnfX2dyTnW5KdaQpb+vAXYi30OkgJOvWrsjMOo DUF7BFOA5dFx/rr8Tm8869l7n/Q787g= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-638-Df7aMRMXPwetv5BMFZ5S4g-1; Mon, 11 Mar 2024 06:41:12 -0400 X-MC-Unique: Df7aMRMXPwetv5BMFZ5S4g-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E6832803CF0; Mon, 11 Mar 2024 10:41:11 +0000 (UTC) Received: from [10.39.194.148] (unknown [10.39.194.148]) by smtp.corp.redhat.com (Postfix) with ESMTP id 72A8E112131D; Mon, 11 Mar 2024 10:41:11 +0000 (UTC) Message-ID: Date: Mon, 11 Mar 2024 10:41:10 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 To: Shiro B , gdb@sourceware.org References: From: Andrew Dinn Subject: Re: Inquiry on AArch64 Simulator in GDB In-Reply-To: X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-GB Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Shiro B, I believe a lot of the simulator code is based on work that was originally done by me when we used the simulator to port OpenJDK to run on AArch64. It was adapted by Phil Muldoon for use in gdb but a lot of the code still looks recognisable to me. I cannot properly answer all your questions but I can provide some background that might help. The original simulator was built to allow execution of AArch64 code generated by the OpenJDK JIT compiler before any hardware was available. So, it was based on a pre-release copy of the ARM ARM (ARM Architecture Reference Manual) and it only catered for the subset of the original instruction set that might be used during operation of conventional userspace application. It did cover all the standard GPR- and FPR-based instructions. I think it may also have supported a small subset of Neon vector instructions. It did not cater for instructions, and associated registers, that would only be needed during system bootstrap (e.g. only a few move to/from system register options are supported). It also does not correctly implement the AArch64 memory model - the original sim provided a per-thread memory cache to simulate a local memory buffer but it was nothing like the real thing. So, memory reads and writes operate using host memory semantics (e.g. TSO on x86). I am not certain but I think the version currently in the gdb tree has been updated to allow for extra Neon vector instructions that were not in the original decode/execute tree. I don't think it has been updated to cater for the few recent additions to the instruction set, nor to allow for SVE. I cannot say exactly what is implemented now. It looks like it still only really addresses userspace programs. I can tell you how to find out fairly quickly and easily what parts of the instruction set are implemented. Start by looking at routine *aarch64_decode_and_execute* in file simulator.c. It gets called from *aarch64_step/run* to decode and execute a single instruction. The decode does a recursive descent through groups and subgroups of instructions, based on a hierarchy of discriminant bits. So, the top level dispatch is on bits [28..25]. Within each top level group different bit patterns are used to do the next dispatch and so on. For example, instructions in top level groups GROUP_DPIMM_1000 and GROUP_DPIMM_1001 are discriminated by looking at bits [25..23] (n.b. it may be obvious but just to spell it out -- the numbers in those top level enum tags indicate what value bits [28..25] have). The logic of this recursive dispatch is implemented by the functions in simulator.c with names in the format dexAAAAAA (A is an Alphabetic character). The corresponding top level and nested bit patterns they rely on are defined by enums with names in the format DispatchAAAA in file decode.h. The function and enum names should match up. So, if you follow through each of these functions and associated nested bit patterns you can find all the instructions in a given family and subfamily that are implemented by the sim. Likewise if you want to see if an instruction is implemented then you need to read off the bit patterns from the top level on downwards to place it in a family and subfamilies. When you reach the bottom of the dexAAAA tree you will find out whether it is catered for or treated as an unknown instruction. Sorry that does not answer all your questions. Hopefully the comments in the code will still help you identify what is supported and how. If they are not enough then I may be able to answer specific queries. However, since I wrote the original code 12 years ago I'm not sure I will be able to remember all the details. regards, Andrew Dinn ----------- Red Hat Distinguished Engineer Red Hat UK Ltd Registered in England and Wales under Company Registration No. 03798903 Directors: Michael Cunningham, Michael ("Mike") O'Neill On 11/03/2024 03:34, Shiro B via Gdb wrote: > Dear GDB Mailing List, > > I hope this message finds you well. I am reaching out to express my keen > interest in the AArch64 simulator included within GDB. (the one in > [binutils-gdb.git]/sim/aarch64/) > > Despite my efforts, I have encountered difficulty in locating detailed > documentation or introductions that shed light on several aspects of this > simulator. > > My inquiries primarily revolve around its capabilities and limitations with > regard to the ARM64 instruction set. > > Specifically, I am eager to understand: > > 1. Which ARM64 instructions are supported by the AArch64 simulator? > 2. Which version of the ARM standard does it adhere to? like v8 v8.1...? > 3. Are there any extensions to the instruction set that the simulator > supports? like pauth, crypto, neon, etc > 3. Could you provide details on any instructions that are explicitly not > supported? > 4. Is the simulator limited to user-mode instructions, or does it offer > broader functionality? > 5. Lastly, I would appreciate insights into any known issues, limitations, > or scenarios where the AArch64 simulator may not be suitable for use. > > I believe understanding these aspects will greatly enhance my ability to > utilize the AArch64 simulator effectively within GDB for development and > testing purposes. Your guidance and any available documentation or > resources on this topic would be immensely valuable. > > Thank you for your time and assistance. I look forward to your response and > any information you can share. > > Best regards >