From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2907 invoked by alias); 12 Jul 2005 16:16:37 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 2174 invoked by uid 22791); 12 Jul 2005 16:16:26 -0000 Received: from fra-del-01.spheriq.net (HELO fra-del-01.spheriq.net) (195.46.51.97) by sourceware.org (qpsmtpd/0.30-dev) with ESMTP; Tue, 12 Jul 2005 16:16:26 +0000 Received: from fra-out-02.spheriq.net (fra-out-02.spheriq.net [195.46.51.130]) by fra-del-01.spheriq.net with ESMTP id j6CGGO8N012762 for ; Tue, 12 Jul 2005 16:16:24 GMT Received: from fra-cus-02.spheriq.net (fra-cus-02.spheriq.net [195.46.51.38]) by fra-out-02.spheriq.net with ESMTP id j6CGGLQR030277 for ; Tue, 12 Jul 2005 16:16:23 GMT Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by fra-cus-02.spheriq.net with ESMTP id j6CGGEDt025000 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=OK); Tue, 12 Jul 2005 16:16:16 GMT Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9849FDA44; Tue, 12 Jul 2005 16:16:13 +0000 (GMT) Received: by zeta.dmz-eu.st.com (STMicroelectronics, from userid 60012) id 7BF7547531; Tue, 12 Jul 2005 16:18:13 +0000 (GMT) Received: from zeta.dmz-eu.st.com (localhost [127.0.0.1]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3DA4475969; Tue, 12 Jul 2005 16:18:13 +0000 (UTC) Received: from mail1.bri.st.com (mail1.bri.st.com [164.129.8.218]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B66654751A; Tue, 12 Jul 2005 16:18:12 +0000 (GMT) Received: from terrorhawk.bri.st.com (terrorhawk.bri.st.com [164.129.15.13]) by mail1.bri.st.com (MOS 3.4.4-GR) with ESMTP id BPC01220 (AUTH "andrew stubbs"); Tue, 12 Jul 2005 17:16:11 +0100 (BST) Date: Tue, 12 Jul 2005 16:16:00 -0000 To: "Marcel Moolenaar" , "Daniel Jacobowitz" Subject: Re: Invalid registers Cc: GDB References: <20050711154926.GB30937@nevyn.them.org> <94cbbbf6ad84e632126e7a0e59830425@cup.hp.com> From: Andrew STUBBS Content-Type: text/plain; format=flowed; delsp=yes; charset=iso-8859-15 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Message-ID: In-Reply-To: <94cbbbf6ad84e632126e7a0e59830425@cup.hp.com> User-Agent: Opera M2/8.01 (Win32, build 7642) X-O-General-Status: No X-O-Spam1-Status: Not Scanned X-O-Spam2-Status: Not Scanned X-O-URL-Status: Not Scanned X-O-Virus1-Status: No X-O-Virus2-Status: Not Scanned X-O-Virus3-Status: No X-O-Virus4-Status: No X-O-Virus5-Status: Not Scanned X-O-Image-Status: Not Scanned X-O-Attach-Status: Not Scanned X-SpheriQ-Ver: 2.2.3 X-SW-Source: 2005-07/txt/msg00138.txt.bz2 On Mon, 11 Jul 2005 19:47:01 +0100, Marcel Moolenaar wrote: > Given that registers are available when a value has been supplied, > it's logical to assume (a priori) that a register is unavailable > when no value has been supplied. A register's valid "bit" allows > for this since there are 2 states that indicate unavailability: > One that indicates a temporary state (0) and one that indicates a > permanent state (-1). The initial state of a register is the temporarily > unavailable state, which triggers fetching the register from the > target. The target can change the state to permanently unavailable > or supply the value (it can also, theoretically at least, leave the > state unmodified and not provide a value). Hence, the a priori > assumption that registers are unavailable when no value has been > supplied (i.e. when the valid "bit" is not 1) seems to yield good > behaviour when implemented as such. I would say then that gdb knows > when a value is not available. Thanks, I did look at this before I posted, but I concluded that I was not what I was looking for. I mean, how would the target know what frame you were in? I do not know what it means for a register to be invalid in the target. Might it be because some registers are not available when, for example, the FPU is disabled? In any case, my target is always happy to supply registers. Andrew Stubbs