From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 3A9FC3858033; Tue, 1 Feb 2022 15:26:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3A9FC3858033 From: "cvs-commit at gcc dot gnu.org" To: glibc-bugs@sourceware.org Subject: [Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM Date: Tue, 01 Feb 2022 15:26:35 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: glibc X-Bugzilla-Component: libc X-Bugzilla-Version: 2.34 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: RESOLVED X-Bugzilla-Resolution: FIXED X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: 2.34 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: glibc-bugs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-bugs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 15:26:35 -0000 https://sourceware.org/bugzilla/show_bug.cgi?id=3D28033 --- Comment #4 from cvs-commit at gcc dot gnu.org --- The release/2.32/master branch has been updated by H.J. Lu : https://sourceware.org/git/gitweb.cgi?p=3Dglibc.git;h=3D77317b3b0df3170575e= 135be01e9554261c43b8a commit 77317b3b0df3170575e135be01e9554261c43b8a Author: H.J. Lu Date: Wed Jun 30 10:47:06 2021 -0700 x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] From =20=20=20 https://www.intel.com/content/www/us/en/support/articles/000059422/processo= rs.html * Intel TSX will be disabled by default. * The processor will force abort all Restricted Transactional Memory (R= TM) transactions by default. * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcod= e is forcing RTM abort. * On processors that enumerate support for RTM, the CPUID enumeration b= its for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue= to be set by default after microcode update. * Workloads that were benefited from Intel TSX might experience a change in performance. * System software may use a new bit in Model-Specific Register (MSR) 0x= 10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware = Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled. 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. This fixes BZ #28033. (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec) --=20 You are receiving this mail because: You are on the CC list for the bug.=