[Bug ports/28872] Building glibc for MIPSel single float targets

["adhemerval.zanella at linaro dot org" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=28872

--- Comment #16 from Adhemerval Zanella <adhemerval.zanella at linaro dot org> ---
(In reply to Den from comment #15)
> (In reply to Adhemerval Zanella from comment #14)
> 
> Zanella, thank you for your support.
> 
> > In fact it does exactly what I suggested ... on comment #5.
> 
> Well, your patches here just replaces l.d to ldc1 and s.d to sdc1, but as I
> replied to your comment#5, the opcodes sdc1/ldc1 (the almost same load/store
> double but from/to coprocessor1) are not supported for single float targets
> as well. What about lwc1/swc1 and BYTES_PER_WORD? - doubles will not be
> doubles after those instructions, right?
> 
> By the way, you made a mistake in setjmp_aux.c (s.d and sdc1 instead of l.d
> and ldc1). Moreover, the files.c (at least them) can not be compiled when
> there are such presentations of LDFPR/STFPR inside asm volatiles. I suppose
> you just showed a quick realization.
> 
> > $ mips64-linux-gnu/bin/mips64-glibc-linux-gnu-gcc -mabi=32 -mips2
> > -mhard-float -mfpxx t.c -o t
> 
> Please, while tests, additionally use flag -msingle-float and/or -mfp32
> instead of -mfpxx

I am confused because in some places you refers to r5900 and other r6000. AFAIK
r6000 was never supported on Linux [1], and it seems that gcc also does not
fully support the r6010 floating point controller:

$ cat test.c
void foo (double *m, double v)
{
  *m = v;
}
$ mips64el-glibc-linux-gnu-gcc -O2 -mabi=32 -march=r6000 -mfp32 -msingle-float
-mhard-float test.c -S -o -
        .file   1 "test.c"
        .section .mdebug.abi32
        .previous
        .nan    legacy
        .module singlefloat
        .module nooddspreg
        .abicalls
        .option pic0
        .text
        .align  2
        .globl  foo
        .set    nomips16
        .set    nomicromips
        .ent    foo
        .type   foo, @function
foo:
        .frame  $sp,0,$31               # vars= 0, regs= 0/0, args= 0, gp= 0
        .mask   0x00000000,0
        .fmask  0x00000000,0
        .set    noreorder
        .set    nomacro
        sw      $6,0($4)
        jr      $31
        sw      $7,4($4)
[...]

So gcc does not transform double stores to 'swc1', it seems to be using softfp
in this case.

In an case, I think you can try replace LDFPR and STFPR on my patch to the with
'lwc1' and 'swc1' if __mips_fpr is 32.  Something like:

  #if __mips_fpr == 0 || __mips_fpr == 64
  # define STFPR sdc1
  #else if __mips_fpr == 32
  # define STFPR swc1
  #else
  # define STFPR s.d
  #endif

Assuming that the mips machine ou are targetting have the same set of floating
-point registers.

[1] https://www.linux-mips.org/wiki/R6000

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