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From: "adhemerval.zanella at linaro dot org"
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Subject: [Bug ports/28872] Building glibc for MIPSel single float targets
Date: Mon, 07 Mar 2022 11:07:44 +0000
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https://sourceware.org/bugzilla/show_bug.cgi?id=3D28872

--- Comment #21 from Adhemerval Zanella <adhemerval.zanella at linaro dot o=
rg> ---
(In reply to Den from comment #20)
> (In reply to Adhemerval Zanella from comment #19)
> > sysdeps/mips/__longjmp.c
> > +# if __mips_fpr =3D=3D 0 || __mips_fpr =3D=3D 64
> > +#  define LDFPR "ldc1 "
> > +# elif __mips_fpr =3D=3D 32
> > +#  define LDFPR "lwc1 "
> > +# else
> > +#  define LDFPR "l.d "
> > +# endif
> > +  asm volatile (LDFPR "$f20, %0" : : "m" (env[0].__fpregs[0]));
> > ...
> Those LDFPR macroses inside "asm volatile" are not replaced with their lo=
gic
> definition. That will not do the trick for the .c files, so they can not =
be
> compiled (as the compiler "thinks" that it is ldfpr opcode). The trick mi=
ght
> be working with .s files.

What do you mean 'replaced with their logic definition' here? For '__mips_f=
pr
=3D=3D 32' is lwc1 used to restore the floating-point state, which afaiu th=
is is
the expected intructions to load the for machines which does not contain do=
uble
precision.

>=20
> The bad thing for me is that I obtained that currently there is no a
> suitable toolchain with the newest binutils and gcc to build a stable
> working cross-compiler for either r6000 with single-float (when using dou=
ble
> it is OK) or r5900 - that kind of the cross-compiler generates malfunctio=
ns
> somewhere...

Can't you use the expected compiler-flags (-O2 -mabi=3D32 -mfp32 -msingle-f=
loat
-mhard-float) along with a recent gcc/binutils?

> So, I can not check with a test whenever your patch, your suppose about
> saving/restoring fp state to/from 32bit registers just by using swc1/lwc1
> "intrusions" in the current ABI realization, is correct or wrong. Because=
 I
> have nothing stable to be sure in, to compare with.

--=20
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