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From: "fantasquex at gmail dot com" <sourceware-bugzilla@sourceware.org>
To: glibc-bugs@sourceware.org
Subject: [Bug build/29501] Check failed on stdlib/tst-strfrom while building for RISCV64 on a unmatched hardware
Date: Sun, 11 Sep 2022 15:34:02 +0000	[thread overview]
Message-ID: <bug-29501-131-tcxu2Lv1u6@http.sourceware.org/bugzilla/> (raw)
In-Reply-To: <bug-29501-131@http.sourceware.org/bugzilla/>

https://sourceware.org/bugzilla/show_bug.cgi?id=29501

--- Comment #5 from Letu Ren <fantasquex at gmail dot com> ---
As mentioned in 11.3 section of the latest RISC-V ISA manual 20191213, 

Except when otherwise stated, if the result of a floating-point operation is
NaN, it is the canonical NaN. The canonical NaN has a positive sign and all
significand bits clear except the MSB, a.k.a. the quiet bit. For
single-precision floating-point, this corresponds to the pattern 0x7fc00000.

And in section 6.3 of the latest version of IEEE 754 which is published in
2019,

When either an input or result is a NaN, this standard does not interpret the
sign of a NaN.

So, I think the problem is that IEEE 754 doesn't care about the sign bit of
NAN. And RISC-V ISA follows IEEE 754 and sets the default sign bit of NAN to
positive. The test case fails. Maybe we can change the test case a little bit,
since the sign bit of NAN doesn't matter?

BTW, I'm interested in "hook" you mentioned. Which part of code should I take a
look?

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       reply	other threads:[~2022-09-11 15:34 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <bug-29501-131@http.sourceware.org/bugzilla/>
2022-09-11 15:34 ` fantasquex at gmail dot com [this message]
2022-09-12 17:39 ` joseph at codesourcery dot com
2022-09-15 16:11 ` fantasquex at gmail dot com
2022-10-28 14:49 ` cvs-commit at gcc dot gnu.org
2022-10-28 16:35 ` adhemerval.zanella at linaro dot org

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