From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 82AA73835DE6; Tue, 30 Aug 2022 14:35:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 82AA73835DE6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1661870119; bh=S5Ld8XjX3MUKrFz1Qa8jNZk+zMB1hNXOGtV6JQGw3+Y=; h=From:To:Subject:Date:In-Reply-To:References:From; b=EB76p1clzNrR8fjSbA4cHQSDbk7QPWGtJBTrcuHNpLQUq+Qj/3RrXC9OURBw/G/r4 rAK/EtB1CXK/C/BM4n1APsPnJ3Pbqas1BtV8IuZNuH67O4ilhTNVPqHresMx44Ikaz 3LkHuOv4+P5t6B1YD/qKwVRGb44zBm/Gb7iwjmss= From: "adhemerval.zanella at linaro dot org" To: glibc-bugs@sourceware.org Subject: [Bug libc/29537] [2.34 regression]: Alignment issue on m68k when using futexes on qemu-user Date: Tue, 30 Aug 2022 14:35:19 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: glibc X-Bugzilla-Component: libc X-Bugzilla-Version: 2.34 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: adhemerval.zanella at linaro dot org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D29537 --- Comment #5 from Adhemerval Zanella --- (In reply to Carlos O'Donell from comment #3) > (In reply to Adhemerval Zanella from comment #2) > > It seems a real issue, but I am puzzled why we have not see any issue so > > far. I take mostly runs were done in single-core, where hardware did not > > enforce 32-bit alignment with atomic operations. > >=20 > > A better change would be to use: > >=20 > > diff --git a/sysdeps/nptl/libc-lockP.h b/sysdeps/nptl/libc-lockP.h > > index d3a6837fd2..9efe962588 100644 > > --- a/sysdeps/nptl/libc-lockP.h > > +++ b/sysdeps/nptl/libc-lockP.h > > @@ -34,7 +34,7 @@ > > #include > >=20 > > /* Mutex type. */ > > -typedef int __libc_lock_t; > > +typedef int __libc_lock_t __LOCK_ALIGNMENT; > > typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t; > > typedef pthread_rwlock_t __libc_rwlock_t; >=20 > Does this impact any externally visible ABIs? >=20=20 > > Since __LOCK_ALIGNMENT is defined per architecture if required. The HP= PA > > also requires a 16-byte alignment for locks, although it is just a > > historical artifact to keep compatibility with old implementation. >=20 > If an architecture needs higher alignment for locks then I strongly sugge= st > out-of-line locking in the kernel as we did for parisc. We have an array = of > locks that we use to scale the futex locking operations. We pick a lock > based on the low-bit hash of the futex address, and we use that consisten= tly > in our kernel helper (kernel aided emulation of compare-and-swap) and ins= ide > the kernel. This yields a consistent behaviour on SMP where the userspace > CAS uses the same set of lock words for the address as the kernel-side fu= tex > CAS. Those lock words are 16-byte aligned because only load-and-clear-word > (ldcw) exists on parisc and requires the extra alignment for the hardware > atomicity to hold. I was not aware of HPPA limitation, it seems that we will need to propagate= it to internal locks as well.=20=20 The m68k issues, afaiu, is different because int has a 2-byte alignment on m68k: $ cat test.c _Static_assert (_Alignof (int) =3D=3D 4, "_Alignof (int) !=3D 4"); $ x86_64-linux-gnu-gcc test.c -c $ /home/azanella/toolchain/install/compilers/m68k-linux-gnu/bin/m68k-glibc-li= nux-gnu-gcc test.c -c test.c:1:1: error: static assertion failed: "_Alignof (int) !=3D 4" 1 | _Static_assert (_Alignof (int) =3D=3D 4, "_Alignof (int) !=3D 4"); | ^~~~~~~~~~~~~~ And futex syscall enforces 4-bytes alignments for the input addresses (as Andreas noted). --=20 You are receiving this mail because: You are on the CC list for the bug.=