From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 5E3B73839076; Tue, 30 Aug 2022 14:16:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5E3B73839076 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1661868989; bh=26a47L/LA1Bd2jz94A8zhjhp7VMfFLDqiDbrA00dQOc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=CHvygk8KSGtBqENrqmxIjbnjUR9Oet3kc/mLzwWS7NDxLh3UaxPWyI6tFKLd59/UF T9S8zJJMmip/W7llXSEnUVy/7tcmDeBOJd42R4w+bjgjq+f/T7ihuqbQd+BekPLAXI L1G7+BeFMFO6MtfkFSUKtbbzfZFg23+BTNtm2i8U= From: "carlos at redhat dot com" To: glibc-bugs@sourceware.org Subject: [Bug libc/29537] [2.34 regression]: Alignment issue on m68k when using futexes on qemu-user Date: Tue, 30 Aug 2022 14:16:28 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: glibc X-Bugzilla-Component: libc X-Bugzilla-Version: 2.34 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: carlos at redhat dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D29537 Carlos O'Donell changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |carlos at redhat dot com --- Comment #3 from Carlos O'Donell --- (In reply to Adhemerval Zanella from comment #2) > It seems a real issue, but I am puzzled why we have not see any issue so > far. I take mostly runs were done in single-core, where hardware did not > enforce 32-bit alignment with atomic operations. >=20 > A better change would be to use: >=20 > diff --git a/sysdeps/nptl/libc-lockP.h b/sysdeps/nptl/libc-lockP.h > index d3a6837fd2..9efe962588 100644 > --- a/sysdeps/nptl/libc-lockP.h > +++ b/sysdeps/nptl/libc-lockP.h > @@ -34,7 +34,7 @@ > #include >=20 > /* Mutex type. */ > -typedef int __libc_lock_t; > +typedef int __libc_lock_t __LOCK_ALIGNMENT; > typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t; > typedef pthread_rwlock_t __libc_rwlock_t; Does this impact any externally visible ABIs? > Since __LOCK_ALIGNMENT is defined per architecture if required. The HPPA > also requires a 16-byte alignment for locks, although it is just a > historical artifact to keep compatibility with old implementation. If an architecture needs higher alignment for locks then I strongly suggest out-of-line locking in the kernel as we did for parisc. We have an array of locks that we use to scale the futex locking operations. We pick a lock bas= ed on the low-bit hash of the futex address, and we use that consistently in o= ur kernel helper (kernel aided emulation of compare-and-swap) and inside the kernel. This yields a consistent behaviour on SMP where the userspace CAS u= ses the same set of lock words for the address as the kernel-side futex CAS. Th= ose lock words are 16-byte aligned because only load-and-clear-word (ldcw) exis= ts on parisc and requires the extra alignment for the hardware atomicity to ho= ld. --=20 You are receiving this mail because: You are on the CC list for the bug.=