[Bug libc/30037] glibc 2.34 and newer segfault if CPUID leaf 0x2 reports zero

["decui at microsoft dot com" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=30037

Dexuan Cui <decui at microsoft dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |decui at microsoft dot com

--- Comment #1 from Dexuan Cui <decui at microsoft dot com> ---
I'm reading "Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 2A: Instruction Set Reference, A-L" for the definition of CPUID leaf
0x2: 

"
INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX

When CPUID executes with EAX set to 02H, the processor returns information
about the processor’s internal TLBs, cache and prefetch hardware in the EAX,
EBX, ECX, and EDX registers. The information is reported in encoded form and
fall into the following categories:

• The least-significant byte in register EAX (register AL) will always return
01H. Software should ignore this value and not interpret it as an informational
descriptor.

• The most significant bit (bit 31) of each register indicates whether the
register contains valid information (set to 0) or is reserved (set to 1).

• If a register contains valid information, the information is contained in 1
byte descriptors. There are four types of encoding values for the byte
descriptor, the encoding type is noted in the second column of Table 3-12.
Table
3-12 lists the encoding of these descriptors. Note that the order of
descriptors in the EAX, EBX, ECX, and EDX registers is not defined; that is,
specific bytes are not designated to contain descriptors for specific cache,
prefetch, or TLB types. The descriptors may appear in any order. Note also a
processor may report a general descriptor type (FFH) and not report any byte
descriptor of “cache type” via CPUID leaf 2.

"

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