From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 9332A3858C30; Mon, 17 Jul 2023 08:46:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9332A3858C30 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1689583569; bh=mpRt81PoqgHBkzdX6ANQyK96k5o9oXzDePQ8kvNpBaU=; h=From:To:Subject:Date:In-Reply-To:References:From; b=wH8unY1M+EV97j+6DmbfpmgpxcGWkP4x9Els3Ytt4A0Yw1Hsyf0jtrH+VvD12PhPx Nzxc29Oc9uVbEixPcce5yogSBJXbIIuFENZdHcVbjNqgctV/t99pX8naPf+YWVSAyA zgeMPQDgZyb5q+CKyYzii/6Ct+C5n0mERuj9sK70= From: "fweimer at redhat dot com" To: glibc-bugs@sourceware.org Subject: [Bug libc/30643] Missing cache information on x86-64 under Intel TDX Date: Mon, 17 Jul 2023 08:46:07 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: glibc X-Bugzilla-Component: libc X-Bugzilla-Version: unspecified X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: fweimer at redhat dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: security- X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D30643 Florian Weimer changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |fweimer at redhat dot com --- Comment #1 from Florian Weimer --- Raised on libc-alpha and elsewhere: Missing cache information on x86-64 under Intel TDX (glibc bug 30643) This quick hack produces more reasonable values: # bash testrun.sh posix/getconf -a | grep CACHE LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 49152 LEVEL1_DCACHE_ASSOC 12 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 16 LEVEL2_CACHE_LINESIZE 64 LEVEL3_CACHE_SIZE 110100480 LEVEL3_CACHE_ASSOC 15 LEVEL3_CACHE_LINESIZE 64 LEVEL4_CACHE_SIZE 0 LEVEL4_CACHE_ASSOC=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 LEVEL4_CACHE_LINESIZE=20=20=20=20=20=20=20=20=20=20=20=20=20=20 diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index c98fa57a..814a314b 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -271,6 +271,10 @@ handle_intel (int name, const struct cpu_features *cpu_features) unsigned int edx; __cpuid (2, eax, ebx, ecx, edx); + if (eax =3D=3D 0 && ebx =3D=3D 0 && ecx =3D=3D 0 && edx =3D=3D 0) + /* Redirect to other information source for Intel TDX. */ + eax =3D 0xff; + /* The low byte of EAX in the first round contain the number of rounds we have to make. At least one, the one we are already doing. */ --=20 You are receiving this mail because: You are on the CC list for the bug.=