From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id EAA6C385842A; Mon, 23 Oct 2023 14:28:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EAA6C385842A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1698071285; bh=AW2SRr8m+EOkP6hXqqYFKjhSQ/rUKl4q+7kkIVs7rY8=; h=From:To:Subject:Date:In-Reply-To:References:From; b=bLnE4XZvdls/jVBu0Cpdp1wUs3xmr+a1b0yQfr+HWTg1vBWWe3k+MzoM7vuRTLmOe 7pxXwUBiGAZPUTBqkmkEzUoqWGcyfhJPoVl4Mhbc9h+xdIR4u0euqzos850g6erKh+ x1meeBtQ65i/mUGxnE9lNNQ4jeJYrj37q3biRArk= From: "bruno at clisp dot org" To: glibc-bugs@sourceware.org Subject: [Bug math/30988] fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le Date: Mon, 23 Oct 2023 14:28:05 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: glibc X-Bugzilla-Component: math X-Bugzilla-Version: 2.37 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: bruno at clisp dot org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D30988 --- Comment #3 from Bruno Haible --- (In reply to Adhemerval Zanella from comment #2) > Indeed, this seems to be an unexpected side-effect of how we implement the > GNU extension feenableexcept There's no better way, IMO, to implement feenableexcept. The problem really comes from the hardware. > Maybe something like: >=20 > diff --git a/sysdeps/powerpc/fpu/fesetexcept.c > b/sysdeps/powerpc/fpu/fesetexcept.c > index 609a148a95..e5396daf44 100644 > --- a/sysdeps/powerpc/fpu/fesetexcept.c > +++ b/sysdeps/powerpc/fpu/fesetexcept.c > @@ -29,6 +29,10 @@ fesetexcept (int excepts) > /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */ > | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) > & FE_INVALID_SOFTWARE)); > + > + if (u.l & FPSCR_ENABLES_MASK) > + return -1; > + > if (n.l !=3D u.l) > { > fesetenv_register (n.fenv); This patch has the drawback of failing even in some situations that it could handle. For example, if trapping on FE_DIVBYZERO is enabled and someone cal= ls fesetexcept (FE_INVALID), there is no reason to fail. I would therefore sug= gest this patch instead: diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..5137df7ba1 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,13 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l !=3D u.l) { + if (n.l & (exceptions >> FPSCR_EXCEPT_TO_ENABLE_SHIFT)) + { + /* Setting the exception flags may trigger a trap. + ISO C 23 =C2=A7 7.6.4.4 does not allow it. */ + return 1; + } + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips= .=20 */ --=20 You are receiving this mail because: You are on the CC list for the bug.=