From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id D60093858D38; Sun, 22 Oct 2023 22:31:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D60093858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1698013906; bh=kAPLLzpOBVN8iELoKspnBfiB8OMmifbsdMIKN+g8I5g=; h=From:To:Subject:Date:From; b=Xpmvqc5DmMeUxmiWnbF6vNjjLxitwJC/ilWapXwqfPAng/w5FxVdV5Y+q2qvVO8en u31oMf+9szHZlwbkcLwAZLp2AFZq+mo7/SgTv30KRf/EyghUA3De1/cHmeUp0OgOs0 l2l4hD4OGTU/WCOYmQAbE17+vQ4WvLMV3F14bmSM= From: "bruno at clisp dot org" To: glibc-bugs@sourceware.org Subject: [Bug math/30988] New: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le Date: Sun, 22 Oct 2023 22:31:46 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: glibc X-Bugzilla-Component: math X-Bugzilla-Version: 2.37 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: bruno at clisp dot org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at sourceware dot org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone attachments.created Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://sourceware.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://sourceware.org/bugzilla/show_bug.cgi?id=3D30988 Bug ID: 30988 Summary: fesetexcept raises floating-point exception traps on ppc, ppc64, ppc64le Product: glibc Version: 2.37 Status: UNCONFIRMED Severity: normal Priority: P2 Component: math Assignee: unassigned at sourceware dot org Reporter: bruno at clisp dot org Target Milestone: --- Created attachment 15187 --> https://sourceware.org/bugzilla/attachment.cgi?id=3D15187&action=3Ded= it test case foo.c According to ISO C 23 =C2=A7 7.6.4.4, fesetexcept is supposed to set floati= ng-point exception flags without raising a trap. (Unlike feraiseexcept, which is supposed to raise a trap if feenableexcept() was called with the appropriate argument.) "This function changes the state of the floating-point exception flags, b= ut does not cause any other side effects that might be associated with raising floating-point exceptions. 267) Footnote 267) Implementation extensions like traps for floating-point exceptions and IEC 60559 exception handling do not occur." That's not how glibc's implementation does it on powerpc, powerpc64, and ppc64le. How to reproduce: 1. Compile the attached program foo.c. $ gcc -Wall foo.c -lm or for the 32-bit powerpc architecture: $ gcc -m32 -Wall foo.c -lm 2. Run it. $ ./a.out Floating point exception 3. Run it under gdb. $ gdb a.out=20 (gdb) run Starting program: /home/haible/a.out=20 [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/powerpc64le-linux-gnu/libthread_db.so= .1". Program received signal SIGFPE, Arithmetic exception. fesetexcept (excepts=3D536870912) at ../sysdeps/powerpc/fpu/fesetexcept.c:34 34 ../sysdeps/powerpc/fpu/fesetexcept.c: No such file or directory. (gdb) x/i $pc =3D> 0x7ffff7e21070 : mtfsf 255,f0,1 I think it is a hardware limitation that on PowerPC CPUs, setting a floating-point exception flag triggers a trap, when traps are enabled for the particular exception and globally for the thread (via prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE)). See "PowerPC User Instruction Set Architecture" Book I Version 2.01 , p. 90: "In this architecture, if software is to be notified that a given kind of exception has occurred, the corre- sponding FPSCR exception enable bit must be set to 1 and a mode other than Ignore Exceptions Mode must be used. In this case the system floating-point enabled exception error handler is invoked if an enabled floating-point exception occurs. The system floating-point enabled exception error handler is also invoked if a Move To FPSCR instruction causes an exception bit and the corresponding enable bit both to be 1; the Move To FPSCR instruction is considered to cause the enabled exception." In this situation, I would expect the fesetexcept() function to return a non-zero value (as error indicator) and not modify the FPSCR register. --=20 You are receiving this mail because: You are on the CC list for the bug.=