From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2101) id CB76339540BC; Wed, 22 Apr 2020 22:15:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CB76339540BC Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alistair Francis To: glibc-cvs@sourceware.org Subject: [glibc/alistair/rv32.next] RISC-V: The ABI implementation for 32-bit X-Act-Checkin: glibc X-Git-Author: Zong Li X-Git-Refname: refs/heads/alistair/rv32.next X-Git-Oldrev: 70e3d09f439b569ee0dabf7c5d336928897bdbe2 X-Git-Newrev: 6bcee67ccdccb244515cefbb0d2f4835b1613da2 Message-Id: <20200422221554.CB76339540BC@sourceware.org> Date: Wed, 22 Apr 2020 22:15:54 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Apr 2020 22:15:54 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=6bcee67ccdccb244515cefbb0d2f4835b1613da2 commit 6bcee67ccdccb244515cefbb0d2f4835b1613da2 Author: Zong Li Date: Fri Nov 30 17:16:18 2018 +0800 RISC-V: The ABI implementation for 32-bit This patch adds the ABI implementation about 32 bit version. It contains the Linux-specific and RISC-V architecture code, I've collected here. Diff: --- sysdeps/riscv/bits/wordsize.h | 4 +- sysdeps/riscv/nptl/bits/pthreadtypes-arch.h | 10 ++++- sysdeps/riscv/nptl/bits/struct_rwlock.h | 27 ++++++++++++- sysdeps/riscv/sfp-machine.h | 27 ++++++++++++- sysdeps/riscv/sys/asm.h | 5 ++- sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h | 53 ++++++++++++++++++++++++++ 6 files changed, 121 insertions(+), 5 deletions(-) diff --git a/sysdeps/riscv/bits/wordsize.h b/sysdeps/riscv/bits/wordsize.h index faccc71828..ee430d9036 100644 --- a/sysdeps/riscv/bits/wordsize.h +++ b/sysdeps/riscv/bits/wordsize.h @@ -25,5 +25,7 @@ #if __riscv_xlen == 64 # define __WORDSIZE_TIME64_COMPAT32 1 #else -# error "rv32i-based targets are not supported" +# define __WORDSIZE_TIME64_COMPAT32 0 +# define __WORDSIZE32_SIZE_ULONG 0 +# define __WORDSIZE32_PTRDIFF_LONG 0 #endif diff --git a/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h b/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h index c3c72d6c10..363034c38a 100644 --- a/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h +++ b/sysdeps/riscv/nptl/bits/pthreadtypes-arch.h @@ -32,7 +32,15 @@ # define __SIZEOF_PTHREAD_BARRIER_T 32 # define __SIZEOF_PTHREAD_BARRIERATTR_T 4 #else -# error "rv32i-based systems are not supported" +# define __SIZEOF_PTHREAD_ATTR_T 32 +# define __SIZEOF_PTHREAD_MUTEX_T 32 +# define __SIZEOF_PTHREAD_MUTEXATTR_T 4 +# define __SIZEOF_PTHREAD_COND_T 48 +# define __SIZEOF_PTHREAD_CONDATTR_T 4 +# define __SIZEOF_PTHREAD_RWLOCK_T 48 +# define __SIZEOF_PTHREAD_RWLOCKATTR_T 8 +# define __SIZEOF_PTHREAD_BARRIER_T 20 +# define __SIZEOF_PTHREAD_BARRIERATTR_T 4 #endif #define __LOCK_ALIGNMENT diff --git a/sysdeps/riscv/nptl/bits/struct_rwlock.h b/sysdeps/riscv/nptl/bits/struct_rwlock.h index acfaa75e1b..b478da0132 100644 --- a/sysdeps/riscv/nptl/bits/struct_rwlock.h +++ b/sysdeps/riscv/nptl/bits/struct_rwlock.h @@ -32,14 +32,39 @@ struct __pthread_rwlock_arch_t unsigned int __writers_futex; unsigned int __pad3; unsigned int __pad4; +#if __riscv_xlen == 64 int __cur_writer; int __shared; unsigned long int __pad1; unsigned long int __pad2; unsigned int __flags; +#else +# if __BYTE_ORDER == __BIG_ENDIAN + unsigned char __pad1; + unsigned char __pad2; + unsigned char __shared; + unsigned char __flags; +# else + unsigned char __flags; + unsigned char __shared; + unsigned char __pad1; + unsigned char __pad2; +# endif + int __cur_writer; +#endif }; -#define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ +#if __riscv_xlen == 64 +# define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, __flags +#else +# if __BYTE_ORDER == __BIG_ENDIAN +# define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, __flags, 0 +# else +# define __PTHREAD_RWLOCK_INITIALIZER(__flags) \ + 0, 0, 0, 0, 0, 0, __flags, 0, 0, 0, 0 +# endif +#endif #endif diff --git a/sysdeps/riscv/sfp-machine.h b/sysdeps/riscv/sfp-machine.h index 08a84fd701..aef8c61a67 100644 --- a/sysdeps/riscv/sfp-machine.h +++ b/sysdeps/riscv/sfp-machine.h @@ -22,7 +22,32 @@ #if __riscv_xlen == 32 -# error "rv32i-based targets are not supported" +# define _FP_W_TYPE_SIZE 32 +# define _FP_W_TYPE unsigned long +# define _FP_WS_TYPE signed long +# define _FP_I_TYPE long + +# define _FP_MUL_MEAT_S(R, X, Y) \ + _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_D(R, X, Y) \ + _FP_MUL_MEAT_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_Q(R, X, Y) \ + _FP_MUL_MEAT_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) + +# define _FP_MUL_MEAT_DW_S(R, X, Y) \ + _FP_MUL_MEAT_DW_1_wide (_FP_WFRACBITS_S, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_DW_D(R, X, Y) \ + _FP_MUL_MEAT_DW_2_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) +# define _FP_MUL_MEAT_DW_Q(R, X, Y) \ + _FP_MUL_MEAT_DW_4_wide (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) + +# define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm (S, R, X, Y) +# define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_2_udiv (D, R, X, Y) +# define _FP_DIV_MEAT_Q(R, X, Y) _FP_DIV_MEAT_4_udiv (Q, R, X, Y) + +# define _FP_NANFRAC_S _FP_QNANBIT_S +# define _FP_NANFRAC_D _FP_QNANBIT_D, 0 +# define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0 #else diff --git a/sysdeps/riscv/sys/asm.h b/sysdeps/riscv/sys/asm.h index bd2de17e17..e314133ce4 100644 --- a/sysdeps/riscv/sys/asm.h +++ b/sysdeps/riscv/sys/asm.h @@ -26,7 +26,10 @@ # define REG_S sd # define REG_L ld #elif __riscv_xlen == 32 -# error "rv32i-based targets are not supported" +# define PTRLOG 2 +# define SZREG 4 +# define REG_S sw +# define REG_L lw #else # error __riscv_xlen must equal 32 or 64 #endif diff --git a/sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h b/sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h new file mode 100644 index 0000000000..7e48f24345 --- /dev/null +++ b/sysdeps/unix/sysv/linux/riscv/jmp_buf-macros.h @@ -0,0 +1,53 @@ +/* jump buffer constants for RISC-V + Copyright (C) 2017-2020 Free Software Foundation, Inc. + + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +/* Produced by this program: + + #include + #include + #include + #include + + int main (int argc, char **argv) + { + printf ("#define JMP_BUF_SIZE %d\n", sizeof (jmp_buf)); + printf ("#define JMP_BUF_ALIGN %d\n", __alignof__ (jmp_buf)); + printf ("#define SIGJMP_BUF_SIZE %d\n", sizeof (sigjmp_buf)); + printf ("#define SIGJMP_BUF_ALIGN %d\n", __alignof__ (sigjmp_buf)); + printf ("#define MASK_WAS_SAVED_OFFSET %d\n", offsetof (struct __jmp_buf_tag, __mask_was_saved)); + printf ("#define SAVED_MASK_OFFSET %d\n", offsetof (struct __jmp_buf_tag, __saved_mask)); + } */ + +#if defined __riscv_float_abi_soft +# define JMP_BUF_SIZE 188 +# define JMP_BUF_ALIGN 4 +# define SIGJMP_BUF_SIZE 188 +# define SIGJMP_BUF_ALIGN 4 +# define MASK_WAS_SAVED_OFFSET 56 +# define SAVED_MASK_OFFSET 60 +#elif defined __riscv_float_abi_double +# define JMP_BUF_SIZE 288 +# define JMP_BUF_ALIGN 8 +# define SIGJMP_BUF_SIZE 288 +# define SIGJMP_BUF_ALIGN 8 +# define MASK_WAS_SAVED_OFFSET 152 +# define SAVED_MASK_OFFSET 156 +#else +# error "Unknown RISC-V floating-point ABI" +#endif