[glibc] powerpc: Fix incorrect cache line size load in memset (bug 26332)

[Florian Weimer <fw@sourceware.org>]

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7650321ce037302bfc2f026aa19e0213b8d02fe6

commit 7650321ce037302bfc2f026aa19e0213b8d02fe6
Author: Florian Weimer <fweimer@redhat.com>
Date:   Mon Aug 3 18:07:19 2020 +0200

    powerpc: Fix incorrect cache line size load in memset (bug 26332)
    
    __GLRO loaded the word after the requested variable on big-endian
    PowerPC, where LOWORD is 4.  This can cause the memset implement
    go wrong because the masking with the cache line size produces
    wrong results, particularly if the loaded value happens to be 1.
    
    The __GLRO macro is not used in any place where loading the lower
    32-bit word of a 64-bit value is desired, so the +4 offset is always
    wrong.
    
    Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc
    ("powerpc: Move cache line size to rtld_global_ro") and bug 26332.
    
    Reviewed-by: Carlos O'Donell <carlos@redhat.com>

Diff:
---
 sysdeps/powerpc/powerpc32/sysdep.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sysdeps/powerpc/powerpc32/sysdep.h b/sysdeps/powerpc/powerpc32/sysdep.h
index 2ba009e919..829eec266a 100644
--- a/sysdeps/powerpc/powerpc32/sysdep.h
+++ b/sysdeps/powerpc/powerpc32/sysdep.h
@@ -179,8 +179,8 @@ GOT_LABEL:			;					      \
 #else
 /* Position-dependent code does not require access to the GOT.  */
 # define __GLRO(rOUT, rGOT, member, offset)				\
-	lis     rOUT,(member+LOWORD)@ha;					\
-	lwz     rOUT,(member+LOWORD)@l(rOUT)
+	lis     rOUT,(member)@ha;					\
+	lwz     rOUT,(member)@l(rOUT)
 #endif	/* PIC */
 
 #endif	/* __ASSEMBLER__ */