From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1039) id 9F9263861000; Fri, 9 Oct 2020 19:37:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9F9263861000 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: H.J. Lu To: glibc-cvs@sourceware.org Subject: [glibc] : Add Intel UINTR support X-Act-Checkin: glibc X-Git-Author: H.J. Lu X-Git-Refname: refs/heads/master X-Git-Oldrev: bb5fd5ce64b598085bdb8a05cb53777480fe093c X-Git-Newrev: 7674695cf7e28528be7243ceb30c9a600bbaa7b5 Message-Id: <20201009193728.9F9263861000@sourceware.org> Date: Fri, 9 Oct 2020 19:37:28 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Oct 2020 19:37:28 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7674695cf7e28528be7243ceb30c9a600bbaa7b5 commit 7674695cf7e28528be7243ceb30c9a600bbaa7b5 Author: H.J. Lu Date: Thu Oct 8 08:19:15 2020 -0700 : Add Intel UINTR support Add Intel UINTR support to . Diff: --- manual/platform.texi | 3 +++ sysdeps/x86/sys/platform/x86.h | 6 +++--- sysdeps/x86/tst-get-cpu-features.c | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/manual/platform.texi b/manual/platform.texi index 95b0ed0642..0dd12a4353 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -583,6 +583,9 @@ using a TSC deadline value. @item @code{TSXLDTRK} -- TSXLDTRK instructions. +@item +@code{UINTR} -- User interrupts. + @item @code{UMIP} -- User-mode instruction prevention. diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h index 2ba6d3c4f2..22bb28449d 100644 --- a/sysdeps/x86/sys/platform/x86.h +++ b/sysdeps/x86/sys/platform/x86.h @@ -241,7 +241,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define bit_cpu_AVX512_4VNNIW (1u << 2) #define bit_cpu_AVX512_4FMAPS (1u << 3) #define bit_cpu_FSRM (1u << 4) -#define bit_cpu_INDEX_7_EDX_5 (1u << 5) +#define bit_cpu_UINTR (1u << 5) #define bit_cpu_INDEX_7_EDX_6 (1u << 6) #define bit_cpu_INDEX_7_EDX_7 (1u << 7) #define bit_cpu_AVX512_VP2INTERSECT (1u << 8) @@ -460,7 +460,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define index_cpu_AVX512_4VNNIW COMMON_CPUID_INDEX_7 #define index_cpu_AVX512_4FMAPS COMMON_CPUID_INDEX_7 #define index_cpu_FSRM COMMON_CPUID_INDEX_7 -#define index_cpu_INDEX_7_EDX_5 COMMON_CPUID_INDEX_7 +#define index_cpu_UINTR COMMON_CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_6 COMMON_CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_7 COMMON_CPUID_INDEX_7 #define index_cpu_AVX512_VP2INTERSECT COMMON_CPUID_INDEX_7 @@ -679,7 +679,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define reg_AVX512_4VNNIW edx #define reg_AVX512_4FMAPS edx #define reg_FSRM edx -#define reg_INDEX_7_EDX_5 edx +#define reg_UINTR edx #define reg_INDEX_7_EDX_6 edx #define reg_INDEX_7_EDX_7 edx #define reg_AVX512_VP2INTERSECT edx diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c index d11eac9853..d160f7c7a1 100644 --- a/sysdeps/x86/tst-get-cpu-features.c +++ b/sysdeps/x86/tst-get-cpu-features.c @@ -182,6 +182,7 @@ do_test (void) CHECK_CPU_FEATURE (AVX512_4VNNIW); CHECK_CPU_FEATURE (AVX512_4FMAPS); CHECK_CPU_FEATURE (FSRM); + CHECK_CPU_FEATURE (UINTR); CHECK_CPU_FEATURE (AVX512_VP2INTERSECT); CHECK_CPU_FEATURE (MD_CLEAR); CHECK_CPU_FEATURE (SERIALIZE);