From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7814) id A5B1D3951E4A; Mon, 16 Aug 2021 17:13:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A5B1D3951E4A Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Fangrui Song To: glibc-cvs@sourceware.org Subject: [glibc/maskray/lld] powerpc64: Check cacheline size before using optimised memset routines X-Act-Checkin: glibc X-Git-Author: Anton Blanchard X-Git-Refname: refs/heads/maskray/lld X-Git-Oldrev: e4ca6de1bc5e4ba3f94cf0c501a293c5bc827b10 X-Git-Newrev: f2a15dd668913c5a1388ba7e1131b25162b2ea75 Message-Id: <20210816171343.A5B1D3951E4A@sourceware.org> Date: Mon, 16 Aug 2021 17:13:43 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Aug 2021 17:13:43 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=f2a15dd668913c5a1388ba7e1131b25162b2ea75 commit f2a15dd668913c5a1388ba7e1131b25162b2ea75 Author: Anton Blanchard Date: Tue Jul 27 15:47:50 2021 +1000 powerpc64: Check cacheline size before using optimised memset routines A number of optimised memset routines assume the cacheline size is 128B, so we better check before using them. Reviewed-by: Tulio Magno Quites Machado Filho Diff: --- sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c | 18 +++++++++++++----- sysdeps/powerpc/powerpc64/multiarch/memset.c | 15 ++++++++++----- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c index 32564c8f1f..a3fdcd43bd 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c +++ b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c @@ -35,6 +35,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, unsigned long int hwcap = GLRO(dl_hwcap); unsigned long int hwcap2 = GLRO(dl_hwcap2); +#ifdef SHARED + int cacheline_size = GLRO(dl_cache_line_size); +#endif /* hwcap contains only the latest supported ISA, the code checks which is and fills the previous supported ones. */ @@ -90,16 +93,21 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX, + && hwcap & PPC_FEATURE_HAS_VSX + && cacheline_size == 128, __memset_power10) #endif - IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07, + IFUNC_IMPL_ADD (array, i, memset, hwcap2 & PPC_FEATURE2_ARCH_2_07 + && cacheline_size == 128, __memset_power8) - IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_06, + IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_06 + && cacheline_size == 128, __memset_power7) - IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_05, + IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_ARCH_2_05 + && cacheline_size == 128, __memset_power6) - IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_POWER4, + IFUNC_IMPL_ADD (array, i, memset, hwcap & PPC_FEATURE_POWER4 + && cacheline_size == 128, __memset_power4) IFUNC_IMPL_ADD (array, i, memset, 1, __memset_ppc)) diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c index c1aa143f60..056e911699 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/memset.c +++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c @@ -43,16 +43,21 @@ libc_ifunc (__libc_memset, # ifdef __LITTLE_ENDIAN__ (hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX) + && hwcap & PPC_FEATURE_HAS_VSX + && GLRO(dl_cache_line_size) == 128) ? __memset_power10 : # endif - (hwcap2 & PPC_FEATURE2_ARCH_2_07) + (hwcap2 & PPC_FEATURE2_ARCH_2_07 + && GLRO(dl_cache_line_size) == 128) ? __memset_power8 : - (hwcap & PPC_FEATURE_ARCH_2_06) + (hwcap & PPC_FEATURE_ARCH_2_06 + && GLRO(dl_cache_line_size) == 128) ? __memset_power7 : - (hwcap & PPC_FEATURE_ARCH_2_05) + (hwcap & PPC_FEATURE_ARCH_2_05 + && GLRO(dl_cache_line_size) == 128) ? __memset_power6 : - (hwcap & PPC_FEATURE_POWER4) + (hwcap & PPC_FEATURE_POWER4 + && GLRO(dl_cache_line_size) == 128) ? __memset_power4 : __memset_ppc);