From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1039) id F2894385B804; Tue, 1 Feb 2022 15:59:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F2894385B804 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: H.J. Lu To: glibc-cvs@sourceware.org Subject: [glibc/release/2.30/master] x86: Black list more Intel CPUs for TSX [BZ #27398] X-Act-Checkin: glibc X-Git-Author: H.J. Lu X-Git-Refname: refs/heads/release/2.30/master X-Git-Oldrev: 071e2bdd850de9387b22b387f5f42e5c7d6668de X-Git-Newrev: 76e30dd44ef7aab743a538dcd4a81761a1f612d9 Message-Id: <20220201155933.F2894385B804@sourceware.org> Date: Tue, 1 Feb 2022 15:59:33 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 15:59:34 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=76e30dd44ef7aab743a538dcd4a81761a1f612d9 commit 76e30dd44ef7aab743a538dcd4a81761a1f612d9 Author: H.J. Lu Date: Fri Jan 14 14:48:01 2022 -0800 x86: Black list more Intel CPUs for TSX [BZ #27398] Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in: https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html This fixes BZ #27398. Reviewed-by: Noah Goldstein (cherry picked from commit 1e000d3d33211d5a954300e2a69b90f93f18a1a1) Diff: --- sysdeps/x86/cpu-features.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 00ca2fe82d..91215f8e23 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -397,11 +397,42 @@ init_cpu_features (struct cpu_features *cpu_features) break; } - /* Disable TSX on some Haswell processors to avoid TSX on kernels that - weren't updated with the latest microcode package (which disables - broken feature by default). */ + /* Disable TSX on some processors to avoid TSX on kernels that + weren't updated with the latest microcode package (which + disables broken feature by default). */ switch (model) { + case 0x55: + if (stepping <= 5) + goto disable_tsx; + break; + case 0x8e: + /* NB: Although the errata documents that for model == 0x8e, + only 0xb stepping or lower are impacted, the intention of + the errata was to disable TSX on all client processors on + all steppings. Include 0xc stepping which is an Intel + Core i7-8665U, a client mobile processor. */ + case 0x9e: + if (stepping > 0xc) + break; + /* Fall through. */ + case 0x4e: + case 0x5e: + { + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for + processors listed in: + +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html + */ +disable_tsx: + cpu_features->cpuid[index_cpu_HLE].reg_HLE + &= ~bit_cpu_HLE; + cpu_features->cpuid[index_cpu_RTM].reg_RTM + &= ~bit_cpu_RTM; + cpu_features->cpuid[index_cpu_RTM_ALWAYS_ABORT].reg_RTM_ALWAYS_ABORT + |= bit_cpu_RTM_ALWAYS_ABORT; + } + break; case 0x3f: /* Xeon E7 v3 with stepping >= 4 has working TSX. */ if (stepping >= 4)