From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2206) id 5F6A4385842B; Mon, 7 Mar 2022 16:55:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5F6A4385842B Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Siddhesh Poyarekar To: glibc-cvs@sourceware.org Subject: [glibc/siddhesh/gai-cleanup2] x86_64: Fix svml_s_acosf16_core_avx512.S code formatting X-Act-Checkin: glibc X-Git-Author: Sunil K Pandey X-Git-Refname: refs/heads/siddhesh/gai-cleanup2 X-Git-Oldrev: 13089d4cf22a117889888224a6ef29ccb580bdc8 X-Git-Newrev: f42415c73669a11e5a9ea91434c980f306a75b6d Message-Id: <20220307165530.5F6A4385842B@sourceware.org> Date: Mon, 7 Mar 2022 16:55:30 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Mar 2022 16:55:30 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=f42415c73669a11e5a9ea91434c980f306a75b6d commit f42415c73669a11e5a9ea91434c980f306a75b6d Author: Sunil K Pandey Date: Fri Mar 4 15:56:59 2022 -0800 x86_64: Fix svml_s_acosf16_core_avx512.S code formatting This commit contains following formatting changes 1. Instructions proceeded by a tab. 2. Instruction less than 8 characters in length have a tab between it and the first operand. 3. Instruction greater than 7 characters in length have a space between it and the first operand. 4. Tabs after `#define`d names and their value. 5. 8 space at the beginning of line replaced by tab. 6. Indent comments with code. 7. Remove redundent .text section. Reviewed-by: Noah Goldstein Diff: --- .../fpu/multiarch/svml_s_acosf16_core_avx512.S | 423 ++++++++++----------- 1 file changed, 211 insertions(+), 212 deletions(-) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_acosf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_acosf16_core_avx512.S index 7708073975..f08d4304fa 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_acosf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_acosf16_core_avx512.S @@ -29,243 +29,242 @@ /* Offsets for data table __svml_sacos_data_internal */ -#define SgnBit 0 -#define OneHalf 64 -#define SmallNorm 128 -#define MOne 192 -#define Two 256 -#define sqrt_coeff_1 320 -#define sqrt_coeff_2 384 -#define poly_coeff_1 448 -#define poly_coeff_2 512 -#define poly_coeff_3 576 -#define poly_coeff_4 640 -#define poly_coeff_5 704 -#define Pi2H 768 -#define PiH 832 +#define SgnBit 0 +#define OneHalf 64 +#define SmallNorm 128 +#define MOne 192 +#define Two 256 +#define sqrt_coeff_1 320 +#define sqrt_coeff_2 384 +#define poly_coeff_1 448 +#define poly_coeff_2 512 +#define poly_coeff_3 576 +#define poly_coeff_4 640 +#define poly_coeff_5 704 +#define Pi2H 768 +#define PiH 832 #include - .text .section .text.exex512,"ax",@progbits ENTRY(_ZGVeN16v_acosf_skx) - pushq %rbp - cfi_def_cfa_offset(16) - movq %rsp, %rbp - cfi_def_cfa(6, 16) - cfi_offset(6, -16) - andq $-64, %rsp - subq $192, %rsp - vmovups __svml_sacos_data_internal(%rip), %zmm5 - vmovups OneHalf+__svml_sacos_data_internal(%rip), %zmm6 - -/* SQ ~ 2*sqrt(Y) */ - vmovups SmallNorm+__svml_sacos_data_internal(%rip), %zmm9 - vmovups MOne+__svml_sacos_data_internal(%rip), %zmm8 - vmovups Two+__svml_sacos_data_internal(%rip), %zmm12 - vmovups sqrt_coeff_1+__svml_sacos_data_internal(%rip), %zmm13 - vmovaps %zmm0, %zmm4 - -/* x = -|arg| */ - vorps %zmm4, %zmm5, %zmm3 - vandps %zmm4, %zmm5, %zmm2 - vmovups sqrt_coeff_2+__svml_sacos_data_internal(%rip), %zmm0 - -/* Y = 0.5 + 0.5*(-x) */ - vfmadd231ps {rn-sae}, %zmm3, %zmm6, %zmm6 - -/* x^2 */ - vmulps {rn-sae}, %zmm3, %zmm3, %zmm7 - vrsqrt14ps %zmm6, %zmm10 - vcmpps $17, {sae}, %zmm9, %zmm6, %k1 - vcmpps $22, {sae}, %zmm3, %zmm8, %k0 - vmovups poly_coeff_4+__svml_sacos_data_internal(%rip), %zmm9 - vminps {sae}, %zmm6, %zmm7, %zmm1 - vmovups poly_coeff_3+__svml_sacos_data_internal(%rip), %zmm7 - vxorps %zmm10, %zmm10, %zmm10{%k1} - vaddps {rn-sae}, %zmm6, %zmm6, %zmm14 - vmulps {rn-sae}, %zmm1, %zmm1, %zmm8 - vmulps {rn-sae}, %zmm10, %zmm10, %zmm11 - vmulps {rn-sae}, %zmm10, %zmm14, %zmm5 - vcmpps $21, {sae}, %zmm6, %zmm1, %k4 - -/* X