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From: Adhemerval Zanella <azanella@sourceware.org> To: glibc-cvs@sourceware.org Subject: [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers Date: Thu, 31 Mar 2022 19:07:42 +0000 (GMT) [thread overview] Message-ID: <20220331190742.06D9B383982E@sourceware.org> (raw) https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7e0ad147e5d347ea60a83c7eafb0bc7a2b514d99 commit 7e0ad147e5d347ea60a83c7eafb0bc7a2b514d99 Author: Adhemerval Zanella <adhemerval.zanella@linaro.org> Date: Tue Mar 15 18:08:21 2022 -0300 aarch64: Use 64-bit variable to access the special registers Diff: --- sysdeps/aarch64/fpu/fpu_control.h | 36 ++++++++++++++++++-------- sysdeps/aarch64/fpu/fraiseexcpt.c | 2 +- sysdeps/aarch64/sfp-machine.h | 2 +- sysdeps/unix/sysv/linux/aarch64/cpu-features.c | 2 +- sysdeps/unix/sysv/linux/aarch64/sysconf.c | 2 +- 5 files changed, 29 insertions(+), 15 deletions(-) diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 764ed5cdbb..8c1746ba8a 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -29,17 +29,31 @@ # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) #else -# define _FPU_GETCW(fpcr) \ - __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) - -# define _FPU_SETCW(fpcr) \ - __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) - -# define _FPU_GETFPSR(fpsr) \ - __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr)) - -# define _FPU_SETFPSR(fpsr) \ - __asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr)) +# define _FPU_GETCW(fpcr) \ + ({ \ + unsigned long int __fpcr; \ + __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (__fpcr)); \ + fpcr = __fpcr; \ + }) + +# define _FPU_SETCW(fpcr) \ + ({ \ + unsigned long int __fpcr = fpcr; \ + __asm__ __volatile__ ("msr fpcr, %0" : : "r" (__fpcr)); \ + }) + +# define _FPU_GETFPSR(fpsr) \ + ({ \ + unsigned long int __fpsr; \ + __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (__fpsr)); \ + fpsr = __fpsr; \ + }) + +# define _FPU_SETFPSR(fpsr) \ + ({ \ + unsigned long int __fpsr = fpsr; \ + __asm__ __volatile__ ("msr fpsr, %0" : : "r" (__fpsr)); \ + }) #endif /* Reserved bits should be preserved when modifying register diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c index bda6144492..2a98307652 100644 --- a/sysdeps/aarch64/fpu/fraiseexcpt.c +++ b/sysdeps/aarch64/fpu/fraiseexcpt.c @@ -23,7 +23,7 @@ int __feraiseexcept (int excepts) { - int fpsr; + unsigned long int fpsr; const float fp_zero = 0.0; const float fp_one = 1.0; const float fp_max = FLT_MAX; diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h index a9ecdbf961..b4b34e98e9 100644 --- a/sysdeps/aarch64/sfp-machine.h +++ b/sysdeps/aarch64/sfp-machine.h @@ -74,7 +74,7 @@ do { \ const float fp_1e32 = 1.0e32f; \ const float fp_zero = 0.0; \ const float fp_one = 1.0; \ - unsigned fpsr; \ + unsigned long int fpsr; \ if (_fex & FP_EX_INVALID) \ { \ __asm__ __volatile__ ("fdiv\ts0, %s0, %s0" \ diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index 41dda8d003..9242b2c60a 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features) cpu_features->midr_el1 = midr; /* Check if ZVA is enabled. */ - unsigned dczid; + uint64_t dczid; asm volatile ("mrs %0, dczid_el0" : "=r"(dczid)); if ((dczid & DCZID_DZP_MASK) == 0) diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c index 665a2bd624..3b4badc671 100644 --- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c +++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c @@ -27,7 +27,7 @@ static long int linux_sysconf (int name); long int __sysconf (int name) { - unsigned ctr; + unsigned long int ctr; /* Unfortunately, the registers that contain the actual cache info (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
next reply other threads:[~2022-03-31 19:07 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-31 19:07 Adhemerval Zanella [this message] -- strict thread matches above, loose matches on Subject: below -- 2024-02-09 17:32 Adhemerval Zanella 2024-02-07 14:07 Adhemerval Zanella 2024-01-29 17:58 Adhemerval Zanella 2023-12-21 18:54 Adhemerval Zanella 2023-09-28 17:52 Adhemerval Zanella 2023-08-30 12:36 Adhemerval Zanella 2023-02-09 19:48 Adhemerval Zanella 2022-10-28 17:41 Adhemerval Zanella 2022-10-04 12:59 Adhemerval Zanella 2022-06-09 21:21 Adhemerval Zanella 2022-06-09 13:17 Adhemerval Zanella 2022-06-03 14:07 Adhemerval Zanella 2022-05-13 14:20 Adhemerval Zanella 2022-05-12 19:34 Adhemerval Zanella 2022-05-10 18:25 Adhemerval Zanella 2022-04-29 14:05 Adhemerval Zanella 2022-04-04 12:55 Adhemerval Zanella 2022-03-29 20:30 Adhemerval Zanella 2022-03-16 18:04 Adhemerval Zanella
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