From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7847) id DC636383942B; Fri, 1 Apr 2022 20:07:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DC636383942B Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Raoni Fassina Firmino To: glibc-cvs@sourceware.org Subject: [glibc/ibm/2.32/master] x86: Black list more Intel CPUs for TSX [BZ #27398] X-Act-Checkin: glibc X-Git-Author: H.J. Lu X-Git-Refname: refs/heads/ibm/2.32/master X-Git-Oldrev: 77317b3b0df3170575e135be01e9554261c43b8a X-Git-Newrev: b1fcaf14fe91a35a21a184623c4f08352f566297 Message-Id: <20220401200750.DC636383942B@sourceware.org> Date: Fri, 1 Apr 2022 20:07:50 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Apr 2022 20:07:51 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=b1fcaf14fe91a35a21a184623c4f08352f566297 commit b1fcaf14fe91a35a21a184623c4f08352f566297 Author: H.J. Lu Date: Fri Jan 14 14:48:01 2022 -0800 x86: Black list more Intel CPUs for TSX [BZ #27398] Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in: https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html This fixes BZ #27398. Reviewed-by: Noah Goldstein (cherry picked from commit 1e000d3d33211d5a954300e2a69b90f93f18a1a1) Diff: --- sysdeps/x86/cpu-features.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index ad135a122b..484efe7a0f 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -518,11 +518,39 @@ init_cpu_features (struct cpu_features *cpu_features) break; } - /* Disable TSX on some Haswell processors to avoid TSX on kernels that - weren't updated with the latest microcode package (which disables - broken feature by default). */ + /* Disable TSX on some processors to avoid TSX on kernels that + weren't updated with the latest microcode package (which + disables broken feature by default). */ switch (model) { + case 0x55: + if (stepping <= 5) + goto disable_tsx; + break; + case 0x8e: + /* NB: Although the errata documents that for model == 0x8e, + only 0xb stepping or lower are impacted, the intention of + the errata was to disable TSX on all client processors on + all steppings. Include 0xc stepping which is an Intel + Core i7-8665U, a client mobile processor. */ + case 0x9e: + if (stepping > 0xc) + break; + /* Fall through. */ + case 0x4e: + case 0x5e: + { + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for + processors listed in: + +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html + */ +disable_tsx: + CPU_FEATURE_UNSET (cpu_features, HLE); + CPU_FEATURE_UNSET (cpu_features, RTM); + CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT); + } + break; case 0x3f: /* Xeon E7 v3 with stepping >= 4 has working TSX. */ if (stepping >= 4)