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* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-05-13 14:15 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-05-13 14:15 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=ba77203bd407ebdd95fc2d61a3dc758c6b8ad732

commit ba77203bd407ebdd95fc2d61a3dc758c6b8ad732
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-10-28 17:37 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-10-28 17:37 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=5a4acc18c68d51f2e065f0360970f69f09f8d2fb

commit 5a4acc18c68d51f2e065f0360970f69f09f8d2fb
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index d8f76a43b5..303cc4e8d0 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -609,8 +609,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,8 +619,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -631,16 +631,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -650,23 +650,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -700,8 +700,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -736,8 +736,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -751,7 +751,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -764,16 +764,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1000,16 +1000,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1038,8 +1038,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1052,12 +1052,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1119,8 +1119,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1191,8 +1191,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1200,8 +1200,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1213,7 +1213,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1224,8 +1224,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1233,14 +1233,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1250,8 +1250,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1294,8 +1294,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1304,7 +1304,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1354,8 +1354,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1387,8 +1387,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1407,8 +1407,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1424,8 +1424,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1459,8 +1459,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1473,16 +1473,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-10-04 12:55 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-10-04 12:55 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=cbfd8db82e72bdf2ef4cb90bb0a64ea27241828c

commit cbfd8db82e72bdf2ef4cb90bb0a64ea27241828c
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-06-09 21:15 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-06-09 21:15 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=297659c661328c6e3e081f9b06e47f4f2a13334f

commit 297659c661328c6e3e081f9b06e47f4f2a13334f
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-06-09 13:11 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-06-09 13:11 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=297659c661328c6e3e081f9b06e47f4f2a13334f

commit 297659c661328c6e3e081f9b06e47f4f2a13334f
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-06-03 14:01 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-06-03 14:01 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=a72ae367f2a7d918c17bc722700df9b81249b95a

commit a72ae367f2a7d918c17bc722700df9b81249b95a
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-05-12 19:28 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-05-12 19:28 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=4da0eeeb1da722da366de5cc1843a2a3eb29e249

commit 4da0eeeb1da722da366de5cc1843a2a3eb29e249
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-05-10 18:19 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-05-10 18:19 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=f9eae4328a3bfda957a5cb34221ccdf578179085

commit f9eae4328a3bfda957a5cb34221ccdf578179085
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-04-29 13:59 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-04-29 13:59 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1c451e08e294bd69d7c145919b3a812d1a96ab1e

commit 1c451e08e294bd69d7c145919b3a812d1a96ab1e
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-04-04 12:49 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-04-04 12:49 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=85039f11468389b671a3c28edde575bd5455fdfe

commit 85039f11468389b671a3c28edde575bd5455fdfe
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-03-31 19:01 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-03-31 19:01 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=543898a0283c2311297069706b7a17c7f0b6812d

commit 543898a0283c2311297069706b7a17c7f0b6812d
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-03-29 20:24 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-03-29 20:24 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=27149e366378b7783c816fb55b7e892f73de9e91

commit 27149e366378b7783c816fb55b7e892f73de9e91
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-03-16 17:59 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-03-16 17:59 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=958b670b71f026ae5eeda5860a1acbc27c9e1a20

commit 958b670b71f026ae5eeda5860a1acbc27c9e1a20
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-03-15 18:37 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-03-15 18:37 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=958b670b71f026ae5eeda5860a1acbc27c9e1a20

commit 958b670b71f026ae5eeda5860a1acbc27c9e1a20
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..8d6681d55d 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh),							\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-03-11 17:21 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-03-11 17:21 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=d99feb045cc5a1053ca5460e29d7f8ffed9a143d

commit d99feb045cc5a1053ca5460e29d7f8ffed9a143d
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..5b1fc3f6c5 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
@ 2022-03-10 19:20 Adhemerval Zanella
  0 siblings, 0 replies; 16+ messages in thread
From: Adhemerval Zanella @ 2022-03-10 19:20 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=6139126cb8836b661c395fd46c3558e9c32c5d80

commit 6139126cb8836b661c395fd46c3558e9c32c5d80
Author: Fangrui Song <maskray@google.com>
Date:   Sun Oct 10 16:06:14 2021 -0700

    stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
    
    An output constraint takes a lvalue. While GCC happily strips the
    incorrect lvalue to rvalue conversion, Clang rejects the code by
    default:
    
        error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions

Diff:
---
 stdlib/longlong.h | 186 +++++++++++++++++++++++++++---------------------------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index 9b89469ac2..5b1fc3f6c5 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 #if defined (__arc__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   : "cc")
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rICal" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
  && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%r" ((USItype) (al)),					\
 	     "rI" ((USItype) (bl)) __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "r" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	   "	addcs	%0, %0, #65536\n"				\
 	   "	adds	%1, %1, %3, lsl #16\n"				\
 	   "	adc	%0, %0, %3, lsr #16"				\
-	   : "=&r" ((USItype) (xh)),					\
-	     "=r" ((USItype) (xl)),					\
+	   : "=&r" (xh),						\
+	     "=r" (xl),							\
 	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
 	   : "r" ((USItype) (a)),					\
 	     "r" ((USItype) (b)) __CLOBBER_CC );			\
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "%rM" ((USItype) (al)),					\
 	     "rM" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rM" ((USItype) (ah)),					\
 	     "rM" ((USItype) (bh)),					\
 	     "rM" ((USItype) (al)),					\
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{l} %3"							\
-	   : "=a" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "rm" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{l} %4"							\
-	   : "=a" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__x86_64__) && W_TYPE_SIZE == 64
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "%1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
-	   : "=r" ((UDItype) (sh)),					\
-	     "=&r" ((UDItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((UDItype) (ah)),					\
 	     "rme" ((UDItype) (bh)),					\
 	     "1" ((UDItype) (al)),					\
 	     "rme" ((UDItype) (bl)))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mul{q} %3"							\
-	   : "=a" ((UDItype) (w0)),					\
-	     "=d" ((UDItype) (w1))					\
+	   : "=a" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((UDItype) (u)),					\
 	     "rm" ((UDItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, dv) \
   __asm__ ("div{q} %4"							\
-	   : "=a" ((UDItype) (q)),					\
-	     "=d" ((UDItype) (r))					\
+	   : "=a" (q),							\
+	     "=d" (r)							\
 	   : "0" ((UDItype) (n0)),					\
 	     "1" ((UDItype) (n1)),					\
 	     "rm" ((UDItype) (dv)))
@@ -597,8 +597,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -607,8 +607,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   /* The cmp clears the condition bit.  */ \
   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -619,16 +619,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
-	   : "=d" ((USItype) (sh)),					\
-	     "=&d" ((USItype) (sl))					\
+	   : "=d" (sh),							\
+	     "=&d" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "d" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -638,23 +638,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if (defined (__mc68020__) && !defined (__mc68060__))
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("mulu%.l %3,%1:%0"						\
-	   : "=d" ((USItype) (w0)),					\
-	     "=d" ((USItype) (w1))					\
+	   : "=d" (w0),							\
+	     "=d" (w1)							\
 	   : "%0" ((USItype) (u)),					\
 	     "dmi" ((USItype) (v)))
 #define UMUL_TIME 45
 #define udiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divu%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
 #define UDIV_TIME 90
 #define sdiv_qrnnd(q, r, n1, n0, d) \
   __asm__ ("divs%.l %4,%1:%0"						\
-	   : "=d" ((USItype) (q)),					\
-	     "=d" ((USItype) (r))					\
+	   : "=d" (q),							\
+	     "=d" (r)							\
 	   : "0" ((USItype) (n0)),					\
 	     "1" ((USItype) (n1)),					\
 	     "dmi" ((USItype) (d)))
@@ -688,8 +688,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -724,8 +724,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "	move%.l	%/d2,%1\n"					\
 	   "	add%.l	%/d1,%/d0\n"					\
 	   "	move%.l	%/d0,%0"					\
-	   : "=g" ((USItype) (xh)),					\
-	     "=g" ((USItype) (xl))					\
+	   : "=g" (xh)),						\
+	     "=g" (xl)							\
 	   : "g" ((USItype) (a)),					\
 	     "g" ((USItype) (b))					\
 	   : "d0", "d1", "d2", "d3", "d4")
@@ -739,7 +739,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__mc68020__) && !defined (__mcpu32__)
 #define count_leading_zeros(count, x) \
   __asm__ ("bfffo %1{%b2:%b2},%0"					\
-	   : "=d" ((USItype) (count))					\
+	   : "=d" (count)						\
 	   : "od" ((USItype) (x)), "n" (0))
 /* Some ColdFire architectures have a ff1 instruction supported via
    __builtin_clz. */
@@ -752,16 +752,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__m88000__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
 	     "rJ" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rJ" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -988,16 +988,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("a %1,%5\n\tae %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "r" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("s %1,%5\n\tse %0,%3"					\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "r" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\
@@ -1026,8 +1026,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	m	r2,%3\n"						\
 "	cas	%0,r2,r0\n"						\
 "	mfs	r10,%1"							\
-	     : "=r" ((USItype) (ph)),					\
-	       "=r" ((USItype) (pl))					\
+	     : "=r" (ph),						\
+	       "=r" (pl)						\
 	     : "%r" (__m0),						\
 		"r" (__m1)						\
 	     : "r2");							\
@@ -1040,12 +1040,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
   do {									\
     if ((x) >= 0x10000)							\
       __asm__ ("clz	%0,%1"						\
-	       : "=r" ((USItype) (count))				\
+	       : "=r" (count)						\
 	       : "r" ((USItype) (x) >> 16));				\
     else								\
       {									\
 	__asm__ ("clz	%0,%1"						\
-		 : "=r" ((USItype) (count))				\
+		 : "=r" (count)						\
 		 : "r" ((USItype) (x)));					\
 	(count) += 16;							\
       }									\
@@ -1107,8 +1107,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ (								\
        "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
-	   : "=r<" ((USItype)(w1)),					\
-	     "=r<" ((USItype)(w0))					\
+	   : "=r<" (w1),						\
+	     "=r<" (w0)							\
 	   : "r" ((USItype)(u)),					\
 	     "r" ((USItype)(v))						\
 	   : "macl", "mach")
@@ -1179,8 +1179,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
     && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "%rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "%rJ" ((USItype) (al)),					\
@@ -1188,8 +1188,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   __CLOBBER_CC)
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
-	   : "=r" ((USItype) (sh)),					\
-	     "=&r" ((USItype) (sl))					\
+	   : "=r" (sh),							\
+	     "=&r" (sl)							\
 	   : "rJ" ((USItype) (ah)),					\
 	     "rI" ((USItype) (bh)),					\
 	     "rJ" ((USItype) (al)),					\
@@ -1201,7 +1201,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
     register USItype __g1 asm ("g1");					\
     __asm__ ("umul\t%2,%3,%1\n\t"					\
 	     "srlx\t%1, 32, %0"						\
-	     : "=r" ((USItype) (w1)),					\
+	     : "=r" (w1),						\
 	       "=r" (__g1)						\
 	     : "r" ((USItype) (u)),					\
 	       "r" ((USItype) (v)));					\
@@ -1212,8 +1212,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	   "udiv\t%3,%4,%0\n\t"						\
 	   "umul\t%0,%4,%1\n\t"						\
 	   "sub\t%3,%1,%1"						\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1221,14 +1221,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__n1)),					\
 	     "r" ((USItype) (__n0)),					\
 	     "r" ((USItype) (__d)))
@@ -1238,8 +1238,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
    instructions scan (ffs from high bit) and divscc.  */
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "r" ((USItype) (u)),					\
 	     "r" ((USItype) (v)))
 #define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1282,8 +1282,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	bl,a 1f\n"							\
 "	add	%1,%4,%1\n"						\
 "1:	! End of inline udiv_qrnnd"					\
-	   : "=r" ((USItype) (q)),					\
-	     "=r" ((USItype) (r))					\
+	   : "=r" (q),							\
+	     "=r" (r)							\
 	   : "r" ((USItype) (n1)),					\
 	     "r" ((USItype) (n0)),					\
 	     "rI" ((USItype) (d))					\
@@ -1292,7 +1292,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #define count_leading_zeros(count, x) \
   do {                                                                  \
   __asm__ ("scan %1,1,%0"                                               \
-	   : "=r" ((USItype) (count))                                   \
+	   : "=r" (count)                                   		\
 	   : "r" ((USItype) (x)));					\
   } while (0)
 /* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1342,8 +1342,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	mulscc	%%g1,0,%%g1\n"						\
 "	add	%%g1,%%o5,%0\n"						\
 "	rd	%%y,%1"							\
-	   : "=r" ((USItype) (w1)),					\
-	     "=r" ((USItype) (w0))					\
+	   : "=r" (w1),							\
+	     "=r" (w0)							\
 	   : "%rI" ((USItype) (u)),					\
 	     "r" ((USItype) (v))						\
 	   : "g1", "o5" __AND_CLOBBER_CC)
@@ -1375,8 +1375,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 "	sub	%1,%2,%1\n"						\
 "3:	xnor	%0,0,%0\n"						\
 "	! End of inline udiv_qrnnd"					\
-	   : "=&r" ((USItype) (__q)),					\
-	     "=&r" ((USItype) (__r))					\
+	   : "=&r" (__q),						\
+	     "=&r" (__r)						\
 	   : "r" ((USItype) (__d)),					\
 	     "1" ((USItype) (__n1)),					\
 	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1395,8 +1395,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "add\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "add\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1412,8 +1412,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 	     "sub\t%r3,%4,%0\n\t"					\
 	     "movcs\t%%xcc, 1, %2\n\t"					\
 	     "sub\t%0, %2, %0"						\
-	     : "=r" ((UDItype)(sh)),				      	\
-	       "=&r" ((UDItype)(sl)),				      	\
+	     : "=r" (sh),				      		\
+	       "=&r" (sl),				      		\
 	       "+r" (__carry)				      		\
 	     : "%rJ" ((UDItype)(ah)),				     	\
 	       "rI" ((UDItype)(bh)),				      	\
@@ -1447,8 +1447,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
 		   "sllx %3,32,%3\n\t"					\
 		   "add %1,%3,%1\n\t"					\
 		   "add %5,%2,%0"					\
-	   : "=r" ((UDItype)(wh)),					\
-	     "=&r" ((UDItype)(wl)),					\
+	   : "=r" (wh),							\
+	     "=&r" (wl),						\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
 	   : "r" ((UDItype)(u)),					\
 	     "r" ((UDItype)(v))						\
@@ -1461,16 +1461,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
 #if defined (__vax__) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "%0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "%1" ((USItype) (al)),					\
 	     "g" ((USItype) (bl)))
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
-	   : "=g" ((USItype) (sh)),					\
-	     "=&g" ((USItype) (sl))					\
+	   : "=g" (sh)),						\
+	     "=&g" (sl)							\
 	   : "0" ((USItype) (ah)),					\
 	     "g" ((USItype) (bh)),					\
 	     "1" ((USItype) (al)),					\


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2022-05-13 14:15 [glibc/azanella/clang] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints Adhemerval Zanella
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