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* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-06-09 21:21 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-06-09 21:21 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=b92b4c785f0590d32725e06c490d02d0c27e38fe

commit b92b4c785f0590d32725e06c490d02d0c27e38fe
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2024-04-02 15:54 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2024-04-02 15:54 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=6ba81b90628125b339bced7e8f52404f3bd1935d

commit 6ba81b90628125b339bced7e8f52404f3bd1935d
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers
    
    clang issues:
    
      error: value size does not match register size specified by the
      constraint and modifier [-Werror,-Wasm-operand-widths]
    
    while tryng to use 32 bit variables with 'mrs' to get/set the
    fpsr, dczid_el0, and ctr.  Since all of 64 bit register, use the
    expected variable size.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 263cf36c05..743c2e5b15 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 5abf498443..c48ba50777 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index c0b047bc0d..4a74ec6bfe 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -128,7 +128,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 6c8216e95a..657df5d845 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2024-02-09 17:32 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2024-02-09 17:32 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=9bc047b8558bfccc58115c30f970eca9a345a621

commit 9bc047b8558bfccc58115c30f970eca9a345a621
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers
    
    clang issues:
    
      error: value size does not match register size specified by the
      constraint and modifier [-Werror,-Wasm-operand-widths]
    
    while tryng to use 32 bit variables with 'mrs' to get/set the
    fpsr, dczid_el0, and ctr.  Since all of 64 bit register, use the
    expected variable size.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 263cf36c05..743c2e5b15 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 5abf498443..c48ba50777 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index b1a3f673f0..b5ab7d51fe 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -87,7 +87,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 6c8216e95a..657df5d845 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2024-02-07 14:07 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2024-02-07 14:07 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=cef28530dc50d397ca764f648268c2d180441348

commit cef28530dc50d397ca764f648268c2d180441348
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers
    
    clang issues:
    
      error: value size does not match register size specified by the
      constraint and modifier [-Werror,-Wasm-operand-widths]
    
    while tryng to use 32 bit variables with 'mrs' to get/set the
    fpsr, dczid_el0, and ctr.  Since all of 64 bit register, use the
    expected variable size.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 263cf36c05..743c2e5b15 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 5abf498443..c48ba50777 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index b1a3f673f0..b5ab7d51fe 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -87,7 +87,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 6c8216e95a..657df5d845 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2024-01-29 17:58 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2024-01-29 17:58 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=a67ae2bf970d5ad71314124911ace76d22a20f93

commit a67ae2bf970d5ad71314124911ace76d22a20f93
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers
    
    clang issues:
    
      error: value size does not match register size specified by the
      constraint and modifier [-Werror,-Wasm-operand-widths]
    
    while tryng to use 32 bit variables with 'mrs' to get/set the
    fpsr, dczid_el0, and ctr.  Since all of 64 bit register, use the
    expected variable size.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 263cf36c05..743c2e5b15 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 5abf498443..c48ba50777 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index b1a3f673f0..b5ab7d51fe 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -87,7 +87,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 6c8216e95a..657df5d845 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2023-12-21 18:54 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2023-12-21 18:54 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=c66b729469850bb4719283184c613bc9adaff1cd

commit c66b729469850bb4719283184c613bc9adaff1cd
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers
    
    clang issues:
    
      error: value size does not match register size specified by the
      constraint and modifier [-Werror,-Wasm-operand-widths]
    
    while tryng to use 32 bit variables with 'mrs' to get/set the
    fpsr, dczid_el0, and ctr.  Since all of 64 bit register, use the
    expected variable size.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 81ed67151b..4bf14c50bb 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 8c674d47d8..1387949ed4 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index c57f154b48..853b9edc24 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -87,7 +87,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index d0fbefa2e9..dcf6cbd68e 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2023-09-28 17:52 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2023-09-28 17:52 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=4ccb9ee9dcb043d4eb77de1ca5e5554fb675805f

commit 4ccb9ee9dcb043d4eb77de1ca5e5554fb675805f
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers
    
    clang issues:
    
      error: value size does not match register size specified by the
      constraint and modifier [-Werror,-Wasm-operand-widths]
    
    while tryng to use 32 bit variables with 'mrs' to get/set the
    fpsr, dczid_el0, and ctr.  Since all of 64 bit register, use the
    expected variable size.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 81ed67151b..4bf14c50bb 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 8c674d47d8..1387949ed4 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index dc09c1c827..bf3196d5e5 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -82,7 +82,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index d0fbefa2e9..dcf6cbd68e 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2023-08-30 12:36 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2023-08-30 12:36 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=e5502a8fad50f0d761a907afc1a336ae151e284a

commit e5502a8fad50f0d761a907afc1a336ae151e284a
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 81ed67151b..4bf14c50bb 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 8c674d47d8..1387949ed4 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index dc09c1c827..bf3196d5e5 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -82,7 +82,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index d0fbefa2e9..dcf6cbd68e 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2023-02-09 19:48 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2023-02-09 19:48 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=fc29c406a27b0f18e7778dec9c08b25945c391fc

commit fc29c406a27b0f18e7778dec9c08b25945c391fc
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 81ed67151b..4bf14c50bb 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index 8c674d47d8..1387949ed4 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 0380f116de..7d5c2aea2c 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index d0fbefa2e9..dcf6cbd68e 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-10-28 17:41 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-10-28 17:41 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=db8710d0b28f7ed6152c2636cb3aa73d54fd3d9b

commit db8710d0b28f7ed6152c2636cb3aa73d54fd3d9b
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 429f4910e7..1fd314fb3d 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index d14c0f4e1f..5b91e1f90a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-10-04 12:59 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-10-04 12:59 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=c756434f6c59c6c63a5e2666d6b0731644065f1b

commit c756434f6c59c6c63a5e2666d6b0731644065f1b
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 429f4910e7..1fd314fb3d 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index d14c0f4e1f..5b91e1f90a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-06-09 13:17 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-06-09 13:17 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=b92b4c785f0590d32725e06c490d02d0c27e38fe

commit b92b4c785f0590d32725e06c490d02d0c27e38fe
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-06-03 14:07 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-06-03 14:07 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=e7f9d34ac325db3c3c5552962c6c317512e81568

commit e7f9d34ac325db3c3c5552962c6c317512e81568
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-05-13 14:20 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-05-13 14:20 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=303b3d64740c9e5f2e76f59b2c9d2718e1b5703c

commit 303b3d64740c9e5f2e76f59b2c9d2718e1b5703c
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-05-12 19:34 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-05-12 19:34 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=ff311d726b9cf3b3afe185bf84aec79e5d3d6986

commit ff311d726b9cf3b3afe185bf84aec79e5d3d6986
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-05-10 18:25 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-05-10 18:25 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7e90d9a8fdf004d13dd0390b75e1c9472458b2b9

commit 7e90d9a8fdf004d13dd0390b75e1c9472458b2b9
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-04-29 14:05 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-04-29 14:05 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=c5d5a719abc6bffde4c084a269a91153ec937999

commit c5d5a719abc6bffde4c084a269a91153ec937999
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-04-04 12:55 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-04-04 12:55 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=2116e8544f0e21767dd0c1b9a97f4d4c09a7a68a

commit 2116e8544f0e21767dd0c1b9a97f4d4c09a7a68a
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-03-31 19:07 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-03-31 19:07 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7e0ad147e5d347ea60a83c7eafb0bc7a2b514d99

commit 7e0ad147e5d347ea60a83c7eafb0bc7a2b514d99
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-03-29 20:30 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-03-29 20:30 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=b5c199a9531b7ea523ae48faf0ea4db60d65105c

commit b5c199a9531b7ea523ae48faf0ea4db60d65105c
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [glibc/azanella/clang] aarch64: Use 64-bit variable to access the special registers
@ 2022-03-16 18:04 Adhemerval Zanella
  0 siblings, 0 replies; 21+ messages in thread
From: Adhemerval Zanella @ 2022-03-16 18:04 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=d222b6abed0983ba540084ce705251a3260c60fa

commit d222b6abed0983ba540084ce705251a3260c60fa
Author: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date:   Tue Mar 15 18:08:21 2022 -0300

    aarch64: Use 64-bit variable to access the special registers

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h              | 36 ++++++++++++++++++--------
 sysdeps/aarch64/fpu/fraiseexcpt.c              |  2 +-
 sysdeps/aarch64/sfp-machine.h                  |  2 +-
 sysdeps/unix/sysv/linux/aarch64/cpu-features.c |  2 +-
 sysdeps/unix/sysv/linux/aarch64/sysconf.c      |  2 +-
 5 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..8c1746ba8a 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -29,17 +29,31 @@
 # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
 # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
 #else
-# define _FPU_GETCW(fpcr) \
-  __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (fpcr))
-
-# define _FPU_SETCW(fpcr) \
-  __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (fpcr))
-
-# define _FPU_GETFPSR(fpsr) \
-  __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (fpsr))
-
-# define _FPU_SETFPSR(fpsr) \
-  __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (fpsr))
+# define _FPU_GETCW(fpcr)					\
+  ({ 								\
+   unsigned long int __fpcr;					\
+   __asm__ __volatile__ ("mrs	%0, fpcr" : "=r" (__fpcr));	\
+   fpcr = __fpcr;						\
+  })
+
+# define _FPU_SETCW(fpcr)					\
+  ({								\
+   unsigned long int __fpcr = fpcr;				\
+   __asm__ __volatile__ ("msr	fpcr, %0" : : "r" (__fpcr));    \
+  })
+
+# define _FPU_GETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr;					\
+   __asm__ __volatile__ ("mrs	%0, fpsr" : "=r" (__fpsr));	\
+   fpsr = __fpsr;						\
+  })
+
+# define _FPU_SETFPSR(fpsr)					\
+  ({								\
+   unsigned long int __fpsr = fpsr;				\
+   __asm__ __volatile__ ("msr	fpsr, %0" : : "r" (__fpsr));    \
+  })
 #endif
 
 /* Reserved bits should be preserved when modifying register
diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
index bda6144492..2a98307652 100644
--- a/sysdeps/aarch64/fpu/fraiseexcpt.c
+++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
@@ -23,7 +23,7 @@
 int
 __feraiseexcept (int excepts)
 {
-  int fpsr;
+  unsigned long int fpsr;
   const float fp_zero = 0.0;
   const float fp_one = 1.0;
   const float fp_max = FLT_MAX;
diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
index a9ecdbf961..b4b34e98e9 100644
--- a/sysdeps/aarch64/sfp-machine.h
+++ b/sysdeps/aarch64/sfp-machine.h
@@ -74,7 +74,7 @@ do {						\
     const float fp_1e32 = 1.0e32f;					\
     const float fp_zero = 0.0;						\
     const float fp_one = 1.0;						\
-    unsigned fpsr;							\
+    unsigned long int fpsr;						\
     if (_fex & FP_EX_INVALID)						\
       {									\
         __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 41dda8d003..9242b2c60a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -86,7 +86,7 @@ init_cpu_features (struct cpu_features *cpu_features)
   cpu_features->midr_el1 = midr;
 
   /* Check if ZVA is enabled.  */
-  unsigned dczid;
+  uint64_t dczid;
   asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
 
   if ((dczid & DCZID_DZP_MASK) == 0)
diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
index 665a2bd624..3b4badc671 100644
--- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
+++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
@@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
 long int
 __sysconf (int name)
 {
-  unsigned ctr;
+  unsigned long int ctr;
 
   /* Unfortunately, the registers that contain the actual cache info
      (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux


^ permalink raw reply	[flat|nested] 21+ messages in thread

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