From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7844) id 4D51C386C5A0; Thu, 30 Jun 2022 03:03:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4D51C386C5A0 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Noah Goldstein To: glibc-cvs@sourceware.org Subject: [glibc] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments X-Act-Checkin: glibc X-Git-Author: H.J. Lu X-Git-Refname: refs/heads/master X-Git-Oldrev: 58bcf7b71a113378dd490f6c41931a14f25a26c9 X-Git-Newrev: 88070acdd0e21a300a381e3d6ba106ca14285a5f Message-Id: <20220630030346.4D51C386C5A0@sourceware.org> Date: Thu, 30 Jun 2022 03:03:46 +0000 (GMT) X-BeenThere: glibc-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Glibc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Jun 2022 03:03:46 -0000 https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=88070acdd0e21a300a381e3d6ba106ca14285a5f commit 88070acdd0e21a300a381e3d6ba106ca14285a5f Author: H.J. Lu Date: Wed Jun 29 13:42:06 2022 -0700 x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr and wmemchr. Co-authored-by: H.J. Lu Diff: --- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++++++--------------- 1 file changed, 51 insertions(+), 48 deletions(-) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index dcfc237a93..9e07283f86 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -55,26 +55,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/memchr.c. */ IFUNC_IMPL (i, name, memchr, X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memchr_evex) + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memchr_evex) X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memchr_evex_rtm) + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memchr_evex_rtm) X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, - CPU_FEATURE_USABLE (AVX2), - __memchr_avx2) + CPU_FEATURE_USABLE (AVX2), + __memchr_avx2) X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __memchr_avx2_rtm) - /* Can be lowered to V1 if a V2 implementation is added. */ + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __memchr_avx2_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ X86_IFUNC_IMPL_ADD_V2 (array, i, memchr, - 1, - __memchr_sse2)) + 1, + __memchr_sse2)) /* Support sysdeps/x86_64/multiarch/memcmp.c. */ IFUNC_IMPL (i, name, memcmp, @@ -293,26 +294,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */ IFUNC_IMPL (i, name, rawmemchr, X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __rawmemchr_evex) + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __rawmemchr_evex) X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __rawmemchr_evex_rtm) + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __rawmemchr_evex_rtm) X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, - CPU_FEATURE_USABLE (AVX2), - __rawmemchr_avx2) + CPU_FEATURE_USABLE (AVX2), + __rawmemchr_avx2) X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __rawmemchr_avx2_rtm) - /* Can be lowered to V1 if a V2 implementation is added. */ + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __rawmemchr_avx2_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr, - 1, - __rawmemchr_sse2)) + 1, + __rawmemchr_sse2)) /* Support sysdeps/x86_64/multiarch/strlen.c. */ IFUNC_IMPL (i, name, strlen, @@ -756,26 +758,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/wmemchr.c. */ IFUNC_IMPL (i, name, wmemchr, X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __wmemchr_evex) + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __wmemchr_evex) X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __wmemchr_evex_rtm) + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __wmemchr_evex_rtm) X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, - CPU_FEATURE_USABLE (AVX2), - __wmemchr_avx2) + CPU_FEATURE_USABLE (AVX2), + __wmemchr_avx2) X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __wmemchr_avx2_rtm) - /* Can be lowered to V1 if a V2 implementation is added. */ + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __wmemchr_avx2_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr, - 1, - __wmemchr_sse2)) + 1, + __wmemchr_sse2)) /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */ IFUNC_IMPL (i, name, wmemcmp,