From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1778) id F3A013857811; Mon, 3 Oct 2022 21:51:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F3A013857811 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664833869; bh=OXWhUNdWfpgfJSep5RsPha46H+v0kcEywQ1hkNCLWug=; h=From:To:Subject:Date:From; b=Fn2hssYKMU4kltz6eXK/4yTKyZ8sTSdnibN+DdWMFXzebGE7ZcyAybWs97RHdbzHu KcmDzD0VFxst2Q/147uWioLO3mCB7m7z4jeVgoadPq6PpJUqxBf6j3cXFOA+Oza8jg i6l7fePQuHp4NaGLCPk8tkOzKotZmIOxQyANfkgs= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Aurelien Jarno To: glibc-cvs@sourceware.org Subject: [glibc/release/2.36/master] x86-64: Require BMI2 for AVX2 strcmp implementation X-Act-Checkin: glibc X-Git-Author: Aurelien Jarno X-Git-Refname: refs/heads/release/2.36/master X-Git-Oldrev: 46479e5d10ed87825aa277da158d6a687974518b X-Git-Newrev: 7afbd1e56acb721031bffd876f275dcb1af7e530 Message-Id: <20221003215108.F3A013857811@sourceware.org> Date: Mon, 3 Oct 2022 21:51:08 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7afbd1e56acb721031bffd876f275dcb1af7e530 commit 7afbd1e56acb721031bffd876f275dcb1af7e530 Author: Aurelien Jarno Date: Mon Oct 3 23:46:11 2022 +0200 x86-64: Require BMI2 for AVX2 strcmp implementation The AVX2 strcmp implementation uses the 'bzhi' instruction, which belongs to the BMI2 CPU feature. NB: It also uses the 'tzcnt' BMI1 instruction, but it is executed as BSF as BSF if the CPU doesn't support TZCNT, and produces the same result for non-zero input. Partially fixes: b77b06e0e296 ("x86: Optimize strcmp-avx2.S") Partially resolves: BZ #29611 Reviewed-by: Noah Goldstein (cherry picked from commit 4d64c6445735e9b34e2ac8e369312cbfc2f88e17) Diff: --- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 4 +++- sysdeps/x86_64/multiarch/strcmp.c | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index d208fae4bf..a42b0a4620 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -591,10 +591,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, && CPU_FEATURE_USABLE (BMI2)), __strcmp_evex) X86_IFUNC_IMPL_ADD_V3 (array, i, strcmp, - CPU_FEATURE_USABLE (AVX2), + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (BMI2)), __strcmp_avx2) X86_IFUNC_IMPL_ADD_V3 (array, i, strcmp, (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (BMI2) && CPU_FEATURE_USABLE (RTM)), __strcmp_avx2_rtm) X86_IFUNC_IMPL_ADD_V2 (array, i, strcmp, diff --git a/sysdeps/x86_64/multiarch/strcmp.c b/sysdeps/x86_64/multiarch/strcmp.c index fdd5afe3af..9d6c9f66ba 100644 --- a/sysdeps/x86_64/multiarch/strcmp.c +++ b/sysdeps/x86_64/multiarch/strcmp.c @@ -45,12 +45,12 @@ IFUNC_SELECTOR (void) const struct cpu_features *cpu_features = __get_cpu_features (); if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2) && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load, )) { if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) - && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) - && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)) return OPTIMIZE (evex); if (CPU_FEATURE_USABLE_P (cpu_features, RTM))