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From: Aurelien Jarno <aurel32@sourceware.org>
To: glibc-cvs@sourceware.org
Subject: [glibc/release/2.36/master] x86-64: Require BMI2 for AVX2 wcs(n)cmp implementations
Date: Mon,  3 Oct 2022 21:51:19 +0000 (GMT)	[thread overview]
Message-ID: <20221003215119.5ECDC385C8B1@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=d8bf4388df679fa5a3ae7889a649e573e3124530

commit d8bf4388df679fa5a3ae7889a649e573e3124530
Author: Aurelien Jarno <aurelien@aurel32.net>
Date:   Mon Oct 3 23:46:11 2022 +0200

    x86-64: Require BMI2 for AVX2 wcs(n)cmp implementations
    
    The AVX2 wcs(n)cmp implementations use the 'bzhi' instruction, which
    belongs to the BMI2 CPU feature.
    
    NB: It also uses the 'tzcnt' BMI1 instruction, but it is executed as BSF
    as BSF if the CPU doesn't support TZCNT, and produces the same result
    for non-zero input.
    
    Partially fixes: b77b06e0e296 ("x86: Optimize strcmp-avx2.S")
    Partially resolves: BZ #29611
    
    Reviewed-by: Noah Goldstein  <goldstein.w.n@gmail.com>
    (cherry picked from commit f31a5a884ed84bd37032729d4d1eb9d06c9f3c29)

Diff:
---
 sysdeps/x86_64/multiarch/ifunc-impl-list.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index aebef3daaf..fec8790c11 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -810,10 +810,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
 				      && CPU_FEATURE_USABLE (BMI2)),
 				     __wcscmp_evex)
 	      X86_IFUNC_IMPL_ADD_V3 (array, i, wcscmp,
-				     CPU_FEATURE_USABLE (AVX2),
+				     (CPU_FEATURE_USABLE (AVX2)
+				      && CPU_FEATURE_USABLE (BMI2)),
 				     __wcscmp_avx2)
 	      X86_IFUNC_IMPL_ADD_V3 (array, i, wcscmp,
 				     (CPU_FEATURE_USABLE (AVX2)
+				      && CPU_FEATURE_USABLE (BMI2)
 				      && CPU_FEATURE_USABLE (RTM)),
 				     __wcscmp_avx2_rtm)
 	      /* ISA V2 wrapper for SSE2 implementation because the SSE2
@@ -830,10 +832,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
 				      && CPU_FEATURE_USABLE (BMI2)),
 				     __wcsncmp_evex)
 	      X86_IFUNC_IMPL_ADD_V3 (array, i, wcsncmp,
-				     CPU_FEATURE_USABLE (AVX2),
+				     (CPU_FEATURE_USABLE (AVX2)
+				      && CPU_FEATURE_USABLE (BMI2)),
 				     __wcsncmp_avx2)
 	      X86_IFUNC_IMPL_ADD_V3 (array, i, wcsncmp,
 				     (CPU_FEATURE_USABLE (AVX2)
+				      && CPU_FEATURE_USABLE (BMI2)
 				      && CPU_FEATURE_USABLE (RTM)),
 				     __wcsncmp_avx2_rtm)
 	      /* ISA V2 wrapper for GENERIC implementation because the

                 reply	other threads:[~2022-10-03 21:51 UTC|newest]

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