From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1778) id 5118F3858299; Mon, 3 Oct 2022 21:56:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5118F3858299 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664834170; bh=wFzO28nEkz3t6Y0GiGHin9gppkNV5vXTYMvvZDG4LhE=; h=From:To:Subject:Date:From; b=Hl+maRN7ps92gQ3sQZD8gGXm1WmgLo1lcZKKkpHJfz6xKo89lB4PoYAM2FZoIvxmn iDz14L16ivAhDJThFeT/R0yXaWSBnkm3hyaj4s/YOufAPiz4okyDresi7+S9FX/gwF xKmIss+hAaWe0eNiJeFVMVGAxPAbEYSef1aDNtec= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Aurelien Jarno To: glibc-cvs@sourceware.org Subject: [glibc/release/2.35/master] x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation X-Act-Checkin: glibc X-Git-Author: Aurelien Jarno X-Git-Refname: refs/heads/release/2.35/master X-Git-Oldrev: c85a45acacd6f2ecaa66128364e5621e0cdcab1b X-Git-Newrev: 02aa1f4a5b6955f2cb384daa4e520d9c8078a078 Message-Id: <20221003215610.5118F3858299@sourceware.org> Date: Mon, 3 Oct 2022 21:56:10 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=02aa1f4a5b6955f2cb384daa4e520d9c8078a078 commit 02aa1f4a5b6955f2cb384daa4e520d9c8078a078 Author: Aurelien Jarno Date: Mon Oct 3 23:16:46 2022 +0200 x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation The AVX2 memrchr implementation uses the 'shlxl' instruction, which belongs to the BMI2 CPU feature and uses the 'lzcnt' instruction, which belongs to the LZCNT CPU feature. Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S") Partially resolves: BZ #29611 Reviewed-by: Noah Goldstein (cherry picked from commit 3c0c78afabfed4b6fc161c159e628fbf14ff370b) Diff: --- sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 + sysdeps/x86_64/multiarch/ifunc-impl-list.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h index 4289df29ec..5cc1e4b0bc 100644 --- a/sysdeps/x86_64/multiarch/ifunc-avx2.h +++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h @@ -31,6 +31,7 @@ IFUNC_SELECTOR (void) if (CPU_FEATURE_USABLE_P (cpu_features, AVX2) && CPU_FEATURE_USABLE_P (cpu_features, BMI2) + && CPU_FEATURE_USABLE_P (cpu_features, LZCNT) && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load)) { if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index 9959f7b228..a7c8ebbe85 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -192,15 +192,21 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/memrchr.c. */ IFUNC_IMPL (i, name, memrchr, IFUNC_IMPL_ADD (array, i, memrchr, - CPU_FEATURE_USABLE (AVX2), + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (BMI2) + && CPU_FEATURE_USABLE (LZCNT)), __memrchr_avx2) IFUNC_IMPL_ADD (array, i, memrchr, (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (BMI2) + && CPU_FEATURE_USABLE (LZCNT) && CPU_FEATURE_USABLE (RTM)), __memrchr_avx2_rtm) IFUNC_IMPL_ADD (array, i, memrchr, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2) + && CPU_FEATURE_USABLE (LZCNT)), __memrchr_evex) IFUNC_IMPL_ADD (array, i, memrchr, 1, __memrchr_sse2))