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From: Aurelien Jarno <aurel32@sourceware.org> To: glibc-cvs@sourceware.org Subject: [glibc/release/2.33/master] x86: include BMI1 and BMI2 in x86-64-v3 level Date: Mon, 3 Oct 2022 22:04:45 +0000 (GMT) [thread overview] Message-ID: <20221003220445.291D53858D1E@sourceware.org> (raw) https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1480535aa3dd801449644a84a60d015e3cf860fb commit 1480535aa3dd801449644a84a60d015e3cf860fb Author: Aurelien Jarno <aurelien@aurel32.net> Date: Mon Oct 3 23:16:46 2022 +0200 x86: include BMI1 and BMI2 in x86-64-v3 level The "System V Application Binary Interface AMD64 Architecture Processor Supplement" mandates the BMI1 and BMI2 CPU features for the x86-64-v3 level. Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com> (cherry picked from commit b80f16adbd979831bf25ea491e1261e81885c2b6) Diff: --- sysdeps/x86/get-isa-level.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sysdeps/x86/get-isa-level.h b/sysdeps/x86/get-isa-level.h index aa80f56ca6..785c25a835 100644 --- a/sysdeps/x86/get-isa-level.h +++ b/sysdeps/x86/get-isa-level.h @@ -47,6 +47,8 @@ get_isa_level (const struct cpu_features *cpu_features) isa_level |= GNU_PROPERTY_X86_ISA_1_V2; if (CPU_FEATURE_USABLE_P (cpu_features, AVX) && CPU_FEATURE_USABLE_P (cpu_features, AVX2) + && CPU_FEATURE_USABLE_P (cpu_features, BMI1) + && CPU_FEATURE_USABLE_P (cpu_features, BMI2) && CPU_FEATURE_USABLE_P (cpu_features, F16C) && CPU_FEATURE_USABLE_P (cpu_features, FMA) && CPU_FEATURE_USABLE_P (cpu_features, LZCNT)
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